Aldec @ DAC 2017: Presenting Breakthrough Innovations in SoC Design & Verification

Date: 2017/06/06
Type: In the News

Henderson, NV – June 5, 2017 – Aldec, Inc. a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, once again delivers free technical sessions at the Design Automation Conference  (DAC) in Austin, Texas.  


“Aldec will be presenting breakthrough innovations in SoC Design & Verification at DAC,” said Louie De Luna, Aldec Director of Marketing. “We’ll cover Software solutions with Mixed-signal simulation, SystemVerilog DRC, Assertion-based checks for CDC analysis and HW/SW co-simulation with QEMU, Hardware solutions with Emulation in the cloud, Partitioning for prototyping, Hybrid Emulation with QEMU, and Embedded applications with Embedded Vision for Automotive and Industrial IoT.”


Technical Sessions and Demos

June 19-21, 2017 from 10:00am to 6:00pm Booth #421

There is no need to register, each of the following presentations will be offered continuously the Aldec booth throughout the day. Don’t forget to visit our coffee bar while you’re there!

Presentation 01: Industrial IoT Applications: Pick & Place - Embedded Vision & uARM Robot Control and IoT Gateway with Amazon AWS  Read more

Presentation 02: High-Performance Computing (HPC) Applications: Object Movement Detection ViBe™ Algorithm and Genome Short Reads Alignment Read more

Presentation 03: HES Prototyping & Emulation Solutions Read more

Presentation 04:  Embedded Vision Applications for Automotive: ADAS Multi-Camera Surround View and Driver's Face & Eyes Detection Read more

Presentation 05: Continuous Integration Solution for RTL Designs Read more

Presentation 06: Improving Accuracy of RTL DRC and CDC Analysis with Assertions-Based Verification Read more

Presentation 07: Design Rule Checking (DRC) for Common SystemVerilog Design Mistakes Read more

Presentation 08: SoC HW/SW Co-Simulation using QEMU Read more

Presentation 09: Mixed-Signal Simulation with Aldec and Silvaco Read more

Presentation 10: Why Office tools should never be used to manage requirements Read more


Contact or call +1(702)990-4400 for more details.


About DAC

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community of more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area, with approximately 200 of the leading and emerging EDA, silicon, and intellectual property (IP) companies and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic System Design Alliance (ESDA), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design.


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

EE Web: The Benefits of HW/SW Co-Simulation for Zynq-Based Designs

Date: 2017/06/06
Type: In the News

By Adam Taylor


Heterogeneous System-on-Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine high-performance processing systems with state-of-the-art programmable logic. This combination allows the system to be architected to provide an optimal solution. User interfaces, communication, control, and system configuration can be addressed by the Processor System (PS). Meanwhile, the Programmable Logic (PL) can be used to implement low latency, deterministic functions and processing pipelines that exploit its parallel, nature such as those used by image processing and industrial applications.


Communication between the PS and the PL is provided by several memory-mapped interfaces. These interfaces use the Advanced eXtensible Interface (AXI) to provide both Master and Slave communications in each direction...


For the rest of this article, visit EEWeb.


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