Company
Products
Technologies
Events
Support
Downloads
Partners
Design Creation
Schematic / Block Diagram Editor
Code2Graphics
HDL Text Editor
State Machine Editor
FPGA Project Management
IP Core Generator
Testbench Generation
Documentation (HTML/PDF)
Verification
VHDL Simulation
Verilog Simulation
SystemC
SystemVerilog
Assertions (PSL, SVA and OVA)
Verilog Simulation Optimization
Acceleration/Emulation
VHDL Simulation Optimization
Prototyping
Coverage Tools
Design Rule Checker
Specialty Solutions
In-Hardware Simulation
DO-254 Compliance
MATLAB/Simulink Co-Simulation
Verification IP
HDL Regression Manager
NIOS II Co-Verification
ARM Co-Verification
Actel RTAX/RTSX Prototyping
Actel RTSX Prototyping
EDIF Netlist Conversion
Messages
What's New
From Press Room
Aldec® announces Low-cost Linux RTL and Gate-level Simulator
Q4-2009 - Aldec® Design and Verification Newsletter
Upcoming Events
X-fest 2009
Europe: VHDL Coding Tips and Techniques
Technical Documents
DO-254 CTS - Frequently Asked Questions
Verification of Ethernet Designs with SCE-MI based Aldec Emulator