Company
Products
Technologies
Events
Support
Downloads
Partners
Design Creation
Schematic / Block Diagram Editor
Code Browser
Code2Graphics
HDL Text Editor
State Machine Editor
FPGA Project Management
Testbench Generation
Documentation
IP Core Generator
Verification
UVM Transaction Debugging
UVM, OVM and VMM Support
SystemVerilog Simulation
VHDL 2008 Simulation
Simulation Optimization
SystemC Co-Simulation
Assertions and Cover Directives
Phase-Based Linting (PBL)
Acceleration
Emulation
Code Coverage Tools
Mirror-Box Technology
HVD Technology
Design Rule Checker
IP Encryption
Specialty Solutions
DO-254 Tool Qualification
DO-254 In-Hardware Simulation
MATLAB/Simulink Co-Simulation
HDL Regression Manager
ARM/NIOS II Co-Verification
RTAX/RTSX Prototyping
What's New
From Press Room
Aldec 2012 Global Calendar Photo Contest Winners are Announced!
Aldec Confirms Sponsorship of International Conference on Field-Programmable Technology (FPT'11)
Upcoming Events
DVCon
Technical Documents
Debugging SCE-MI Co-Emulation in Riviera-PRO™ Simulation Environment
Introducing Transactions in Design Verification