Extend Vivado Capabilities with Help From the Tcl Store

Xilinx Vivado Tutorial: Upgrade for increased simulation performance

Vince Ibanez, Aldec Corporate Applications Engineer
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Outgrowing something can be hard. So hard, that sometimes we live in denial longer than we should. We are resistant to change, often because we are simply too comfortable with what we know (or too busy) to consider the options.


Sound familiar? For example, if you are like most of today’s verification engineers dealing with increasingly larger designs, it is likely that you have long outgrown your OEM simulator. Chances are also pretty good that your productivity is suffering for it.


If your IDE for FPGA development happens to be Xilinx® Vivado®, thanks to the Xilinx TCL store you have an option to quickly and easily increase your simulation capabilities.


Related Tutorial: Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE


Related YouTube Tutorial: Vivado TCL Store Integration


Most users of Xilinx FPGAs tend to stick with the simulator that comes with Xilinx Vivado. This is wise as Vivado is targeted for a specific device family with optimizations suited for the device that may not be available in other software.


However, sometimes there is a need for high-performance simulation. Some users try a workaround by manually exporting project files into another simulator, then tweaking the design in order to run simulation. Users often find this process simply too buggy, often revert to sticking with the vendor software.


However, with the recent introduction of the TCL store, Xilinx Vivado opened its doors to third-party TCL scripts that can enhance Vivado’s features. With this mechanism, Aldec was able to integrate Active-HDL directly into the Vivado framework. With Xilinx Vivado’s TCL store, integrating Active-HDL simulator in the Vivado work flow is easy. This combination allows users to extend Vivado’s rich synthesis and implementation tool set with Active-HDL’s high performance simulator. This seamless integration eliminates the need to manually map the source files between the two programs as this is all done in the backend.


Here are just some of the benefits from integrating Active-HDL into Xilinx Vivado:

  • Massive increase in simulation performance
  • More comprehensive and up-to-date language support
  • Access to alternative graphical-based design entry methods
  • Ability to create more powerful and robust test benches
  • Support for language interface such as VPI and VHPI
  • Support for assertions
  • The ability to generate coverage reports
  • Access to a rich set of debugging tools
  • Waveform comparison tools
  • Co-simulation with Matlab and Simulink
  • So much more!


Watch the Related YouTube Tutorial: Vivado TCL Store Integration to learn more and about integrating Aldec’s high performance simulator, Active-HDL, with Vivado.

Vince provides support for users of Aldec's Simulation and Verification tools as an Aldec Applications Engineer. He joined Aldec right after graduating from University of Las Vegas, Nevada with a Bachelor’s Degree in Computer Engineering in 2014. His practical experience includes areas in Digital Design, Computer Architecture and Embedded Systems. He holds skills not only in Engineering but in Customer Service as well.


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