Save hours of Place & Route time… in seconds

Vivado Incremental Compile for faster Emulation Setup

Jacek Majkowski, Senior Hardware Engineer
Like(1)  Comments  (0)

Place & Route implementation can sometimes feel like it takes forever. Consider some of these common scenarios:


● After working overtime to create an emulation build for all emulation users, your manager brings you some new drop-in code for one of the modules, meaning you will have to re-run the whole process instead of going home.

● Even worse, you are the guy that has to fix that one module, after realizing that your colleague will be waiting for the emulation build to finish until late into the night.

● Software developers ask you to instrument RTL code with static probes to help find a bug somewhere at the end of the Linux booting process, then stand by and impatiently wait to find the source of the problem, because the software development team has a bet on whether the bug was in hardware or in software.


Just as a watched pot never boils, implementation seems to go on forever in these scenarios.


New HES-DVM features complement Vivado IDE to save Place and Route time

Aldec solutions are designed to save time and money, and now offer valuable new features that complement the Xilinx® Vivado™ Integrated Design Environment (IDE).


The Design Verification Manager (DVM) within the HES-DVM™ HW/SW Validation Platform already offers the capability to implement an incremental design flow, requiring only the recompilation and re-synthesizing of design files that have changed. The partitioning process automatically reuses as much of the existing implementation from the previous run as possible.

But what happens when you have to run a Xilinx Vivado implementation for an FPGA that contains modified module(s)? Fortunately, Xilinx has a nifty little feature called “Vivado Incremental Compile” that HES-DVM supports seamlessly. This feature allows the reuse of as much of the previous place and route implementation as possible.

And because place and route takes the most time of the whole Vivado design implementation flow, there is so much time to save!

Section UG904 of the Xilinx Vivado Design Suite User Guide – Implementation states that “Incremental place and route... can achieve an average of a threefold improvement over normal place and route runtimes when designs have at least 95 percent similar cells, nets, and ports”. However, the remaining 5% of the components in the biggest Xilinx FPGAs used by the Aldec HES emulation system, still equate to quite a big chunk of logic!

On the other hand, if your current emulation build is more revolutionary than evolutionary compared to the previous build, and incremental changes are in more than 20% of the logic, there is no sense in using Vivado Incremental Compile. However, if your current emulation build has only minor changes compared to your previous one, you can simply enable ‘Vivado Incremental Compile’ in the Aldec ‘DVM Generation’ options, saving hours on place and route by reusing the Vivado checkpoint from the last run.


Figure 2. HES-DVM Screenshot ‘DVM Generation’ Options


How does the P&R time savings look in real uses cases?

I obtained preliminary reports from users which confirm savings of 58% to 71% in place and route time. Just take a look at the hard data in Table 1.


Table 1. Place and Route Time Saved with HES-DVM


As always, results are very design-dependent and time-saving figures may vary, but clearly there are numerous scenarios where HES-DVM can shorten emulation setup time by enabling the user to reuse the previous run.

If you’d like to learn more about the time-saving features of HES-DVM, here are two recent webinars you can register to view:

Recorded Webinar: Accelerating The Verification Of Hardware Dependent Software 

Recorded Webinar: SoC Emulation Made Easy/Q&A


About Aldec HES-DVM

HES-DVM is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES-DVM allows for multiple modes of verification and validation including: Simulation Acceleration, Co-emulation and Virtual Modeling, In-Circuit Emulation and Embedded Software and Hardware Co-verification.

Learn more at or contact Aldec Sales at +1-702-990-4400 or

Jacek Majkowski is a Senior Hardware Engineer at Aldec, and a specialist in SCE-MI Co-emulation. Prior to his current role, Jacek spent 7 years in the field of hardware assisted verification. Jacek received his Master of Science in Electrical Engineering from AGH University of Science and Technology in Krakow, Poland.


Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.