Best Design Practices

For High-Capacity FPGA Devices

Dmitry Melnik, Product Manager Software Division
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With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this webinar, we focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues.

Recorded Webinar: Best Design Practices for High-Capacity FPGA Devices

Dmitry Melnik is a product manager at Aldec responsible for ALINT™ and Riviera-PRO™ product lines. He has over 8 years of digital design and verification experience, including previous roles in corporate and field applications, technical marketing, and software development with R&D divisions of Aldec in Europe. Dmitry holds an M.S. in Computer Systems from Kharkiv National University of Radio Electronics, Ukraine.

  • Products:
  • Design Rule Checking


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