UVM Webinar for Hardware Designers "Don't Be Afraid of UVM" Jerry Kaczynski, Research Engineer Like(0) Comments (0) This unintimidating webinar will begin with a solid review of SystemVerilog interfaces with special attention paid to those mysterious Virtual Interfaces, proceeding to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is also explained. The presentation concludes with environment configuration and running test from the top-level module. Watch recorded webinar Attendees not familiar with Object Oriented Programming (OOP) and Transaction-Level Modeling (TLM) are strongly encouraged to view our previously recorded webinars: "Know Your Objects - OOP for Hardware Designers" and "TLM Concepts for Hardware Designers". Visit www.aldec.com/events for additional information about upcoming Aldec events.