Improve Productivity with User-Defined Design Management

Satyam Jani, Product Manager Software Division
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Working with today's complex FPGA projects involves dealing with many different types of HDL files, IPs, libraries, schematics, waveforms etc. Every engineer must juggle these files many times during the FPGA design development phase, and it is critical that FPGA design tools allow users to define and organize the structure of the FPGA project based on user needs. Having the freedom to create user-defined project structures dramatically improves collaboration and productivity.

Related Application Note: User-Defined Design Management
Related YouTube Video: User-defined Design Management in Active-HDL

Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.

  • Products:
  • Active-HDL
  • FPGAデザイン・シミュレーション

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