To Emulate or Prototype?

Is it even a question?

Krzysztof Szczur, Hardware Verification Products Manager
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Recently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask the weaknesses of FPGA prototyping flows. As the Tech Support Manager for Aldec Hardware Emulation Solutions, I have to admit I’ve never had to deploy an army onsite.


It is true that FPGA Prototyping is more challenging than emulation. Yet, for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation.


Emulation also has its benefits that appeal especially to design verification engineers. Aside from the completely automated compilation and setup flow, it offers robust debugging capabilities and a plethora of interfaces that connect the emulator with various verification environments like HDL Simulators, Virtual Platforms, model based design tools (e.g. Matlab and Simulink) or any other environment capable of C/C++ linking.


But wait, do you really need to choose between Emulation and Prototyping?


This may have been true in the 1990s, but a lot has changed since then. FPGA technology has evolved and matured as well as FPGA vendor’s synthesis and place & route software. For some reason however, the big-three of EDA keep it separate. The emulation hardware that is based on custom processors or custom FPGAs is extremely expensive and later, if you need to do prototyping for your design bring-up and firmware development, you wind up with investing more in FPGA-based hardware.


The engineers at Aldec have been working persistently to bridge this gap and unify a hardware platform to be used for both emulation and prototyping. They have developed HES-DVM™, which has evolved over the years to deliver the most cost effective solution.


This effectiveness comes from reusability and scalability.


HES-7™  is the latest generation of prototyping boards that contains largest Virtex®-7 and now Virtex UltraScale™ FPGAs from Xilinx®. These boards are available in various configurations including the backplane board that delivers the ability to scale the whole system up to 633 million ASIC gates (24 Virtex UltraScale 440 chips). The hardware is precisely designed to meet the most restrictive prototyping criteria for clocks distribution or signal integrity. We’ll have the actual boards at our Design Automation Conference (DAC) Booth #619 this year. Please visit to register for a hardware presentation and talk to me personally.


As I have already mentioned, the idea is to reuse the prototyping boards for emulation. What is required for this is:

  1. Automated design compilation,
  2. Debugging capabilities, and
  3. Verification Interfaces.


All of this is included in the HES-DVM software package that allows you to use the HES boards early, when the HDL simulation becomes a verification bottleneck.


The DVM tool provides design setup flow with automatic and guided partitioning, multiple partitions interconnect without limited IO barrier, gated clock conversion, memory mapping and the like. To shrink turnaround times, DVM supports incremental synthesis and implementation.


With the HW Debugger tool, you can fully control your emulation clocks and stop them at any time to inspect your design. You can capture any design signal you like using dynamic debug and save it in the waveform file that can be opened in your simulator’s GUI viewer. This is what we call true RTL debugging, as emulation probes are matched exactly with signals in your RTL code so you can easily find what happens in your design and pinpoint the problem. Moreover the self-checking testbench can probe design signals in the emulator due to the HES Debug API available for the user.


Last but not least, we have various interfaces built upon the PCI Express host and board controller. For simulation acceleration you can choose between direct signal-level or transaction level that is based on Accellera’s SCE-MI. You can use SystemC TLM to integrate emulation with the Virtual Platform or other SystemC testbench or regular C/C++ API to connect your emulated design with any other verification environments. At DAC, we’ll demonstrate the use of SCE-MI Pipes-based interface that was added in HES-DVM recently. If you’d like to learn more about this topic, may I recommend an article, Why I see C in SCE-MI: A Hardware Emulation Guide for Non-C Designers, written by my colleague, Jacek Majkowski.


Undoubtedly Emulation and FPGA Prototyping are converging these days and this process is accelerating due to the tools like HES-DVM. Pure prototyping is still quite difficult to setup when using only FPGA vendor tools, and this is why Aldec is adding prototyping support features to HES-DVM.

If you’d like to learn more, we invite you to call us at +1-702-990-4400 or email

Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining practical experience and deep understanding of design verification methodologies, emulation and physical prototyping. As Hardware Verification Products Manager, Krzysztof cooperates with key customers and Aldec's R&D to overcome complex design verification challenges using Aldec hardware tools and solutions. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland

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