UVM Really is Everywhere

Guest Blog by Doulos CTO, John Aynsley

John Aynsley, Doulos CTO
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According to the official email newsletter sent out in advance of DVCon Europe 2015 in Munich, top of the list of topics for the tutorial day is "Basic UVM, advanced UVM, UVM reuse, all things UVM". This makes me smile, because UVM continues to be one of the hot training topics for us at Doulos. UVM really is everywhere, and that's a good thing because, to cut a long story short, the UVM standard is catalyzing the adoption of coverage-driven verification across a broad community of engineers.

But that's not the end of the story. SystemVerilog is an enormously large and complicated language. UVM is a large and complicated class library. Back in 2011, recognizing the difficulty that many users would face getting to grips with UVM, Doulos first introduced Easier UVM in an attempt to make UVM more accessible to a wider audience. Easier UVM started out as a way of thinking about and learning UVM that would make UVM approachable by ordinary VHDL and Verilog users as well as by verification experts. Since that time, Easier UVM has evolved to become a comprehensive set of UVM coding guidelines and a UVM code generator, which are open and freely available on the web. You can get Easier UVM from www.doulos.com/easier.

It seems the folks at Aldec agree with us that many users will need a helping hand with UVM because they have leveraged the Easier UVM Coding Guidelines in their approach to hardware-assisted acceleration running on their HES-DVM™ emulator. By adapting the code from the Easier UVM Code Generator, Aldec has been able to demonstrate a test environment that is acceleration ready, through the use of the Accellera SCE-MI standard.

You can learn more about Doulos’ Easier UVM and about Aldec’s approach to FPGA co-emulation at DVCon Europe 2015, where both companies will be running tutorials on Wednesday afternoon, November 11th. I will be giving a tutorial (T8) on UVM with special emphasis on how you can use the Easier UVM Code Generator to get examples up-and-running quickly as you learn UVM. Alex Grove from Aldec will be giving a tutorial (T14) on how to get a UVM test environment (written to the Easier UVM Coding Guidelines) accelerated by running parts of it with FPGA co-emulation. You can check out the DVCon Europe Conference Schedule for details. We look forward to seeing you there.

John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specializing in hardware description and verification languages, in particular VHDL, SystemC, SystemVerilog, and now UVM.

John served as technical lead and author of the IEEE Standard 1666-2011 SystemC Language Reference Manual, as well as implementing the 1666-compliance regression test suite for the Accellera Systems Initiative proof-of-concept SystemC simulator. In February 2012 John received the Accellera Systems Initiative Technical Excellence Award in recognition of his contribution to SystemC standardization.

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