LIVE WEBINAR: May 4th, 2016 Getting into SystemVerilog from VHDL: Guidance from a VHDL Guru In this webinar Doulos Senior Member Technical Staff, Doug Perry (author of 'Programming By Example') will provide a VHDL Guru's perspective on SystemVerilog and UVM. Doug will look at the language features of SystemVerilog, contrasting them with what is available in VHDL, and highlighting the challenges of making the transition. Coding examples will be shown running on Aldec Riviera-PRO™. This training webinar will consist of a one-hour broadcast with interactive Q&A available to attendees throughout. Attendance is free of charge. Content Summary: What is SystemVerilog? | Language evolution | Language features Standard verification methodologies | References | Q&A Schedule and Registration: This webinar has two broadcast times to be convenient for international audiences. Please review the times listed below and register for the most appropriate option for your time zone. Wednesday May 4th, 2016: For Europe and Asia Time: 10-11am (BST) | 11am-12pm (CEST) | 3.30-4.30pm (IST) Wednesday May 4th, 2016: For North America (Time: 10-11am (PDT) | 12-1pm (CDT) | 1-2pm (EDT) | 6-7pm (BST) If you have any queries, please contact info@doulos.com. Verifying Large FPGAs Isn't Easy Guest Blog by Doug Perry, Senior Member Technical Staff at Doulos The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages. Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
