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Name Products Type Action
FMC ADAS CARD Technical Specification    
FMC ADAS CARD Overview, Block Diagram, Interfaces, etc.
FMC-ADAS, TySOM™ EDK Technical Specification
Adding Aldec TySOM Board Configurations to Vivado    
Working with Aldec TySOM boards in Vivado requires configuring some parameters of the processing system module and GPIO. Configuration is unique for TySOM-1-7Z030 and TySOM-2-7Z045 boards. This document describes how to obtain and install these configurations in the Vivado tool so users are not required to configure parameters such as voltage levels, memory controllers, and timing delays.
TySOM™ EDK Tutorials
Advanced RTL Debugging for Zynq SoC Designs   
Presenter: Radek Nawrot, Aldec Software Product Manager

Abstract: Designers of complex embedded applications based on Xilinx® Zynq™ device require a high-performance RTL simulation and debugging platform. In this webinar, you will learn several advanced RTL debugging methodologies and techniques that you can employ for your block-level and system level simulation. You will learn how to use Dataflow, Code Coverage, Xtrace and Waveform Contributors for analyzing the errors in your AXI-based Zynq designs.

We welcome you to refer to the following Application Notes prior to the webinar:
Xilinx AXI-Based IP Overview
Simulating AXI BFM Examples Available in Xilinx CORE Generator
Simulating AXI-based Designs in Riviera-PRO
Performing Functional Simulation of Xilinx Zynq BFM in Riviera-PRO

Agenda
  • Embedded development flow between Xilinx Vivado™, SDK™, Riviera-PRO™ and TySOM™
  • Quick introduction to AXI
  • Running Riviera-PRO from Vivado
  • Code Coverage in simulation process
  • Advance dataflow- design overview
  • Bug injection – Xtrace in action
  • Waveform with Contributors – seek bug in code
 Play webinar   
Riviera-PRO, TySOM™ EDK Recorded Webinars
Basic UART Interface Tutorial TySOM-1-7Z030   
In this tutorial, you will learn how to use UART to interface the TySOM-1-7Z030 board with other systems. The UART interface enables us to view serial output from the board which can be useful for monitoring. This project has both a hardware and software part.
TySOM-1, TySOM™ EDK Tutorials
Building and Configuring a Linux OS from Linaro   
This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Analog Devices Linux kernel and Linaro sources for creating a Linux file system
TySOM™ EDK Tutorials
Building and Configuring a Linux OS using the Yocto Project - TySOM-1-7Z030   
This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Yocto project, an open source collaboration project for creating custom Linux-based systems.
TySOM-1, TySOM™ EDK Tutorials
Compiling Xilinx Vivado Simulation Libraries for Riviera-PRO     Riviera-PRO, TySOM™ EDK Application Notes
Creating a Hardware and Software Project to Blink LEDs TySOM -1-7Z030   
In this tutorial, you will learn how to create a hardware project in Xilinx’s Vivado Design Suite and create a software project in Xilinx’s SDK for the TySOM-1-7Z030 board. First you will create the hardware part, then you will create a software application to blink the onboard LEDs using standalone OS. In the Zynq architecture, you are able to implement the design either in a bare metal mode or by using an embedded Linux OS platform.
TySOM-1, TySOM™ EDK Tutorials
Creating a Hardware and Software Project to Blink LEDs using DIP Switches TySOM -1-7Z030   
In this tutorial, you will learn how to create a hardware project in Xilinx’s Vivado Design Suite and create a software project in Xilinx’s SDK for the TySOM-1-7Z030 board. First you will create the hardware part, then you will create a software application to blink the onboard LEDs using onboard switches. At the end of this tutorial, you will also learn how to program the project onto the TySOM-1-7Z030 board using a JTAG programmer. To program the FPGA using a microSD card, you can follow the “Programming the TySOM-1-7Z030 board using a microSD card guide”.
TySOM-1, TySOM™ EDK Tutorials
Designing FPGA-based ADAS Application - Driver Drowsiness Detection   
Advanced Driver Assistance Systems (ADAS) provide a significant contribution to increasing automotive safety. ADAS systems provide the driver with increased situational awareness, helping to reduce collision and accidents. To provide the driver with increased situation awareness ADAS systems can be categorized as providing external or internal awareness. External ADAS systems monitor such aspects as blind spots and lane detection, while internal systems monitor the occupants and particularly the driver themselves such as Driver Drowsiness Detection. Both internal and external ADAS systems rely heavily upon embedded vision systems, implementing these embedded vision systems depending upon the task at hand can be computationally intensive. This computational complexity can reduce the performance of the system introducing latency and reducing the validity of the information provided to the driver. The use of hardware programmable logic enables the implementation of a low latency high performance system. However, industry standard development techniques such as the use of OpenCV cannot be used due to high development cost and timescales. This webinar will demonstrate how an ADAS driver drowsiness detection application can be implemented using a Zynq heterogeneous SoC which combines programmable logic with high performance ARM cores. This example will demonstrate how a System Optimizing Compiler can be used in conjunction with the Zynq to create the ADAS application using high level languages and industry standard frameworks. The use of the System Optimizing Compiler enables seamless acceleration of C functions into the programmable logic, enabling a significant performance increase.  Play webinar   
TySOM Boards, TySOM™ EDK Recorded Webinars
Enabling GPIO Interrupts Tutorial TySOM-1-7Z030   
An interrupt is a signal that temporarily halts the processor’s current activities and demands immediate attention. The processor saves its current state and executes an interrupt service routine to address the reason for the interrupt. Real-time designs require interrupts because many systems will have a number of inputs (e.g. keyboards, mouse, pushbuttons etc.) that will require processing. Inputs from these devices are generally asynchronous to the execution of running processes or tasks, so you cannot always predict when the event will occur. Using interrupts enables the processor to continue processing until an event occurs, at which time the processor can address the event. This interrupt-driven approach also speeds up the response time. This basic GPIO interrupt design is intended to enable GPIO interrupts to users on the TySOM-1-7Z030 board. The standard flow includes several stages to create a hardware platform for the Zynq-7000 based board.
TySOM™ EDK Tutorials
FMC-ADAS Technical Specification    TySOM Boards, FMC-ADAS, TySOM™ EDK Technical Specification
FMC-INDUSTRIAL Technical Specification   
FMC-INDUSTRIAL Technical Specification
TySOM Boards, FMC-INDUSTRIAL, TySOM™ EDK Technical Specification
FMC-INTF Technical Specification    TySOM Boards, FMC-INTF, TySOM™ EDK Technical Specification
FMC-IoT Technical Specification    TySOM Boards, FMC-IOT, TySOM™ EDK Technical Specification
FMC-NET Technical Specification    TySOM Boards, FMC-NET, TySOM™ EDK Technical Specification
FMC-QSFP Technical Specification    TySOM Boards, FMC-QSFP, TySOM™ EDK Technical Specification
FMC-Vision Technical Specification    TySOM Boards, FMC-VISION, TySOM™ EDK Technical Specification
FPGA Accelerator for Genome Aligner - ReneGENE   
Abstract:
Aldec industry partner, ReneLife introduces its proprietary core technology, ReneGENE, for fast and accurate alignment of short reads obtained from the Next Generation Sequencing (NGS) pipeline. The technology, devoid of heuristics can precisely align the DNA reads against a reference genome at a single nucleotide resolution. As genomics permeates the entire landscape of biology, including biomedicine and therapeutics, ReneGENE creates a genomic highway that significantly contributes to reduce the time from sample to information without compromising on accuracy, critical for lifesaving medicare applications, biotechnology product development and forensics.

In this webinar, we present AccuRA, a high-performance reconfigurable FPGA accelerator engine for ReneGENE, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on a 8-core 3.5 GHz AMD FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments. AccuRA offers a need-based affordable solution, deployable both in the cloud and local platforms. AccuRA scales well on the Aldec platform, at multiple levels of design granularity.

Agenda:
  • Introducing the world of genomic big data computing
  • The need for accuracy and precision
  • Introducing ReneGENE/AccuRA
  • Product Demo
  • Impact of ReneGENE-The Genomic Highway
Presenter: Santhi Natarajan, Ph. D (IISc) Play webinar   
Riviera-PRO, HES-DVM, TySOM™ EDK Recorded Webinars
IoT Demo Application Tutorial - TySOM-1-7Z030   
Internet usage has expanded to a new mode: device to device. This new mode is used in Internet of Things (IoT) applications and devices are called IoT gateways. The Aldec TySOM contains a Zynq-7000 SoC with ARM processor and a variety of interfaces to be utilized as an IoT gateway device. This document provides all necessary information about the Aldec IoT demo project with the TySOM-1-7Z030 board.
TySOM-1, TySOM™ EDK Tutorials
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