Resources

Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   

Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a familiar environment to create model behavior.    The objective of any verification framework is to make the Device Under Test (DUT) "feel like" it has been plugged into the board. Hence, the framework must be able to produce the same waveforms and sequences of waveforms that the DUT will see on the board. The OSVVM testbench framework looks identical to other frameworks, including SystemVerilog. It includes verification components (AxiStreamTransmitter and AxiStreamReceiver) and TestCtrl (the test sequencer) as shown in Figure 1. The top level of the testbench connects the components together (using the same methods as in RTL design) and is often called a test harness. Connections between the verification components and TestCtrl use VHDL records (which we call the transaction interface).   Connections between the verification components and the DUT are the DUT interfaces (such as AxiStream, UART, AXI4, SPI, and I2C).   There are three steps required to create an OSVVM verification component: Define the transaction interface (in OSVVM it is a record) Define the transaction procedures (the call API for the test sequencer) Define the internals of the verification component itself.   OSVVM model independent transactions are one of our latest innovations – added to OSVVM in 2020.07. For a class of interfaces, the model independent transactions define the transaction interface and transaction procedures. OSVVM has defined these for address bus interfaces (such as AXI, Avalon, X86, …) and streaming type interfaces (such as UART, AXI Stream, …).    For a testbench/verification component developer, using the model independent transactions allows a developer to focus on just the internals of the verification component. Directive transactions can be copied from models of a similar class. This helps save time in testbench development. For the test case developer, model independent transactions provide address bus interfaces and streaming interfaces with a common set of transactions (API). This makes writing test cases easier since the transaction interface (API) is already familiar.  This also facilitates either re-use of test sequences between different verification components or porting tests from one interface to another.    This webinar provides a guided walk-through of the OSVVM model independent transactions. Benefits of OSVVM OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification.   World-wide, 18% of the FPGA market uses OSVVM [1] – or alternately 36% of the VHDL FPGA market uses OSVVM. In Europe, in the FPGA market, OSVVM (with 36%) leads SystemVerilog+UVM (with 26%).     OSVVM is an innovator and leader in the development of VHDL Verification Methodology. Our approach has been evolving in SynthWorks classes since 1997 and started being released as open source in 2011. So how does it compare to SystemVerilog? Constrained Random – Supported via RandomPkg and coding styles – an OSVVM innovation Functional Coverage – Supported via CoveragePkg – an OSVVM innovation Scoreboards – Supported via ScoreboardGenericPkg – an OSVVM innovation Error reporting and Messaging – supported via AlertLogPkg – concepts borrowed from numerous sources Transaction based testbenches and verification components – in our classes since 1997 Memory Modeling – data structure for efficient creation of memories through sparse allocation. Process Synchronization – barrier synchronization (an OSVVM innovation) as well as other methods. Is OSVVM supported by my simulator? Currently OSVVM is supported by simulators from Mentor, Aldec, Cadence, Synopsys, and GHDL. This is great support and our goal is to keep it this way. When we upgrade existing features in the library, we test to make sure we do not break support within our community. OTOH, when we introduce new capability (generally in separate packages) and there is a significant advantage to using advanced VHDL constructs – such as it simplifies how the item is used, then it is likely we will use it – as a result, some of OSVVM's Verification IP uses records with unconstrained arrays.  We also strictly avoid using deprecated language features - such as shared variables that have an ordinary type. Play webinar   

Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   

The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. Play webinar   

Assertion-based verification (ABV) is the use of assertions for the efficient verification of low-level design specification. These assertions could be verified by simulation and formal verification methods. SystemVerilog Assertions (SVA) standard provides powerful means to express both immediate and concurrent assertions as well as functional coverage constructs. Unlike SystemVerilog, VHDL does not include the concept of concurrent assertions (while VHDL assert statements being similar to immediate assertions in SVA). In this webinar, we will present various methods to implement assertions in VHDL designs as well as identify the strengths and limitations of each method. These methods include PSL (VHDL flavor), the usage of Open Verification Library (OVL) as well as concurrent assertions development using procedural code with assert statements. Play webinar   

Abstract: Experienced users of VHDL simulation with testbenches appreciate additional layer of safety that Coverage Analysis gives them. But are all kinds of coverage equally beneficial? While Code Coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar we will show how to improve quality of the design using Property Coverage and Functional Coverage (with help of OS-VVM). Play webinar   

OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA verification projects from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either simple or complex FPGA blocks. Looking to improve your VHDL FPGA verification methodology? OSVVM is the right solution. We have all the pieces needed for verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them. This webinar provides a broad overview of OSVVM's capabilities. You will learn the OSVVM way of: > Creating a well-structured, testbench framework > Creating verification components (overview – in Part 2 we will cover details) > Creating test cases > Using AffirmIf for self-checking > Using logs for conditional message printing to facilitate debug > Adding constrained random to your tests > Using scoreboards for self-checking > Adding functional coverage > Using Intelligent Coverage Randomization – randomization using a functional coverage model. > Using Alert to add protocol checks > Test Synchronization and Watchdogs > Test Wide Reporting > Using OSVVM's Simulator Independent Scripting (overview – in Part 3 we will cover details) > Creating Test Reports in HTML for Humans > Creating Test Reports in JUnit XML for Continuous Integration OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. > Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.  Play webinar   

Some methodologies (or frameworks) are so complex that you need a script to create the initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM is certainly like this. There are even several organizations that propose that you use their "Lite" or "Easy" approach. Creating a verification component (VC) using OSVVM is simple enough that neither a "Lite" version nor a script is needed. This presentation is a walk through the steps to write a verification component that effectively utilizes OSVVM capabilities. One big time saver in creating OSVVM's VCs is our Model Independent Transactions (MIT). MIT evolved from the observation that many interfaces do the same sort of transactions. For example, Address Bus Interfaces, such as AXI4, Avalon, and Wishbone, all do read and write operations. Similarly, streaming interfaces, such as AxiStream and UARTs, all do send and get operations. OSVVM defines a pattern, or if you prefer an internal standard, for the Address Bus transaction interface and transaction API. It does the same for Stream Interfaces. The result of using OSVVM's MIT is that a VC developer can focus on writing the VC behavior. This makes OSVVM's VC based approach as simple as a "Lite" approach that codes interface behavior in a subprogram. Starting with a VC allows us to include additional capability – such as protocol and timing checkers. VCs also provide a path to greater capability – such as with an AXI4 interface where the Address Write, Write Data, Write Response, Address Read, and Read Data aspects of the interface are independent of each other and need to be handled by separate processes. With a VC, these capabilities can be incrementally added during the test process. At the end of the day, OSVVM does not need a "Lite" version because we make writing verification components as simple as writing a procedure. Nothing more than a template is needed. Any of OSVVM's growing library of verification components can be used as a template. About OSVVM OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. >Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. > OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses > > OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey. [1] https://blogs.sw.siemens.com/verificationhorizons/2020/12/16/part-6-the-2020-wilson-research-group-functional-verification-study/ Play webinar   

According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to simplify debug and help find problems quickly. Scripting can be complicated no matter what language – particularly with EDA tools that need to stay rooted in one directory while it is advantageous to co-locate the user scripts with the verification IP they support. As a result, the scripts must manage the file source locations relative to the simulator directory. Further complicating the scripts is that each simulator API has a different way of specifying commands and command options. No wonder it is frustrating and messy. With OSVVM scripting, it is ok to hate TCL as it is unlikely you will use it directly. OSVVM creates a procedure-based API on top of TCL. User scripts are based on the OSVVM simple simulator command API that uses paths that are relative to the script's location. The messy TCL stuff is handled internally by the OSVVM command API. The result is that scripts include just a little more than a source file list. Generally, the most TCL that user scripts need is a simple if statement – but even this is rare (and there are examples in the OSVVM library). Not meaning to name drop, but OSVVM scripting supports Aldec's Active-HDL and Riviera-PRO, Siemens' ModelSim and QuestaSim, GHDL, Synopsys' VCS, and Cadence's Xcelium. With respect to reports, when we run a set of tests, we need to be able to assess whether all test cases passed or quickly identify which test cases failed. Once we have determined which test case failed, we need to have detailed information for each test case in a separate report that helps reveal the source of the issue. OSVVM's test reporting capability adds another reason as to why OSVVM should be your VHDL Verification Methodology. Our test reporting includes: > An HTML Build Summary Report for human inspection that summarizes the completion status of each test case in a test suite > A JUnit XML Build Summary Report for use with continuous integration (CI/CD) tools. > A separate HTML Test Case Detailed report for each test case with Alert, Functional Coverage, and Scoreboard reports. > An HTML based simulator transcript/log files (simulator output) > A text-based test case transcript file (from OSVVM's TranscriptOpen) > Links to tool generated code coverage reports Why do we go to all this trouble? When OSVVM runs its full regression suite, our build includes 22 test suites with a total of 524 test cases. The log file is 170K lines long. Without good tools we could not easily run our regressions and quickly assess whether it passed or failed. How well does OSVVM work with continuous integration tools? OSVVM uses our scripts and JUnit XML output when running our verification component regression suite on GitHub using GHDL. See https://github.com/OSVVM/OsvvmLibraries/actions. About OSVVM OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. > Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, > > > FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.  Play webinar   

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously in this webinar series. This webinar focuses on advances in OSVVM data structures. OSVVM's Functional Coverage, Scoreboard, FIFO, and Memory data structures are now all based on singletons – in a similar fashion to what is done in AlertLogPkg. Using singletons significantly simplifies each data structure's USER API – the call interface. Specifically, users no longer need to use shared variables, protected types, and their complications. We will discuss the new APIs, their advantages, and some of the improvements OSVVM was able to make by using these. Don't worry though, we still support the older protected type data structures. One of the advantages of the updated data structures was discussed in Part 3 of this webinar series – reports for Functional Coverage and Scoreboards are automatically generated simply by running the tests with OSVVM scripting and calling "EndOfTestReports" rather than "ReportAlerts" at the end of the test. About OSVVM OSVVM is an advanced verification methodology that defines a VHDL verification framework, verification utility library, verification component library, and a scripting flow that simplifies your FPGA or ASIC verification project from start to finish. Using these libraries, you can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that: > Are simple to use and work like built-in language features. > Maximize reuse and reduce project schedule. > Improve readability and reviewability by the whole team including software and system engineers. > Facilitate debug with HTML based test suite and test case reporting. > Support continuous integration (CI/CD) with JUnit XML test suite reporting. > Provide buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering. > Rival the verification capabilities of SystemVerilog + UVM. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 18% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 34%) leads SystemVerilog+UVM (with 26%). Based on the growth in our training, we expect to see improved numbers in the next survey.  Play webinar   

Open Source VHDL Verification Methodology (OSVVM) simplifies and accelerates your FPGA and ASIC verification tasks by providing utility and model (Verification IP) libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. This webinar is a guided walk-through of how to create better self-checking tests using OSVVM utility library and OSVVM model independent transactions. OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification. World-wide, 17% of the FPGA market uses OSVVM [1]. In Europe, OSVVM (with 30%) leads SystemVerilog+UVM (with 20%). Based on the growth in our training, we expect to see improved numbers in the next survey. OSVVM uses a structured, transaction-based test environment – from a high level view the structure is similar to SystemVerilog – although its test harness is structural code, so it is also similar RTL. The similarity to RTL is important. It is what makes OSVVM accessible to RTL as well as verification engineers. In this webinar you will learn the OSVVM Way of: • Using OSVVM model independent transactions to facilitate readability and accelerate test construction • Writing tests with concurrent independent actions – just like your models. • Adding Self-Checking to your tests via OSVVM AffirmIf or scoreboards • Adding conditional message printing to facilitate debug and detailed test for reports via OSVVM logs • Adding constrained random to your tests • Using scoreboards for testing • Adding Protocol Checks to your tests using OSVVM Alert • Test Wide Reporting with a count of WARNING, ERROR, FAILURE, and PASSED for each model • Test Synchronization and Watchdogs Looking to improve your VHDL FPGA verification methodology? OSVVM is the right solution. We have all the pieces needed for verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them. The OSVVM library now part of the IEEE Open Source effort. You can find us at: https://opensource.ieee.org/osvvm. A mirror of OSVVM libraries are hosted on GitHub at: https://github.com/OSVVM/. The presenter, Jim Lewis, is the architect and principal developer of OSVVM. Mr Lewis is also the chair of the IEEE VHDL working group. OSVVM leverages this deep understanding of VHDL to architect a solution that solves difficult problems in a simple way. Is OSVVM supported by my simulator? Currently OSVVM is supported by simulators from Mentor, Aldec, Cadence, Synopsys, and GHDL. This is great support and our goal is to keep it this way. When we upgrade existing features in the library, we test to make sure we do not break support within our community. OTOH, when we introduce new capability (generally in separate packages) and there is a significant advantage to using advanced VHDL constructs – such as it simplifies how the item is used, then it is likely we will use it – as a result, some of OSVVM's Verification IP uses Article Text/Images First 2 sentences of text should summarize the rest of the page. Be brief, today’s readers scan and don’t read large blocks of text/Break up page with images. Highlights Keywords in headers, bold and italicized text, within links and in bullets. records with unconstrained arrays. We also strictly avoid using deprecated language features - such as shared variables that have an ordinary type. Play webinar   

Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. This webinar is a guided walk-through of the OSVVM verification framework and transactions provided by OSVVM models. OSVVM's transaction based testbench approach is the current evolution of the approach taught by SynthWorks' for 20+ years. Looking at its block diagram, you will notice that its architecture looks similar to SystemVerilog + UVM... Play webinar   

Abstract: The issue of securing information flow was very important in the past (mainly in diplomacy and military applications) and became even more important recently, with new applications such as banking (ATM transactions), on-line commerce (e-store transactions), media (pay-per-view contents) and hardware design (secure IP delivery). All those applications face one common problem nicely described in the old joke: the only truly secure information is the one that cannot be read by anybody. Both hardware designers and tool designers must find the balance between security and usability, which can be achieved only by implementing well tested algorithms and workflow. Using Aldec implementation of Secure IP Delivery as the vehicle, this presentation provides informative overview of recommended ciphers and methodologies that can be used by a wide, technical audience.  Play webinar   

Abstract: With the complexity of some FPGA designs now comparable to ASIC, designers are faced with challenging cost, power and functional goals. Leading-edge FPGA designs will now benefit from advanced verification methodologies, but do ASIC-focused EDA vendors offer the best solution? This webinar will explain how Aldec tools are uniquely positioned to efficiently support the verification of complex FPGA designs and how (in combination with the new devices from Lattice) designers can meet their functional, cost and power requirements for complex high volume applications. Play webinar   

Abstract This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing, self-checking tests, messaging, reports, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. The “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development, increase reuse, and reduce maintenance costs. Self-checking is essential in test cases as checking waveform output manually is time consuming, error prone, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection, some of which might be in a different entity) we will need to sum them up and generate an error report. However, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. Messaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities, we need controls that have a wide scope. Furthermore, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. Test reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run, and the OSVVM test case report provides details on the self-checking, functional coverage, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing), these reports help us quickly find which test cases failed and why. The OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. About OSVVM OSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM. Getting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study, in the FPGA market, 66% use VHDL for design, 58% use VHDL for verification, and 28% use OSVVM. Hence, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. Play webinar   

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In part 1 of this webinar series, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally, we will talk about design verification of highly configurable design and IP blocks. Play webinar   

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In part 2 of this webinar series, we will show you important verification patterns providing solutions to repeatable randomization, error management and end-of-test checks. We will also provide an overview of how to define, develop and re-use verification components such as drivers, responders, and monitors. Then, we will talk about how to develop testbenches, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion. Play webinar   

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In this, the concluding episode of the webinar series, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization, functional coverage, and the importance of code coverage to achieve overall design verification completeness. Also, we will provide an overview on other important topics such as assertion and transaction-based verification and debug, static design verification with linting tools and regressions support. Finally, we will talk about ‘Verification Done’, in terms of at what point can the verification be considered complete and how do we achieve it? Play webinar   

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency. The FPGA design architecture also affects several project and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness and verification/test workload.  Play webinar   

For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously. Play webinar