Resources

Finite State Machines (FSM) are a key part of safety-critical design control logic. During the operation of the FPGAs within the systems, single-event upsets or other radiation effects can cause the internal logic to flip to an incorrect value from ‘0’ to ‘1’ or ‘1’ to ‘0’ in a non-deterministic way, causing the system to fail. As transistors shrink, errors are becoming much more common; in a modern chip the devices are so small that cosmic rays or alpha particles can change the value of bits that are stored in FSM registers. In this webinar we will provide the various methods on how to develop robust and safe FSMs - from best practices in FSM design to highly reliable FSM design methods , allowing designers to develop state machines with transient errors detection and correction. Play webinar   

Hardware Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design. Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module. Play webinar   

Cocotb is a CO-routine based CO-simulation Testbench environment for verifying VHDL/Verilog RTL using Python. It is an open-source environment and hosted on Github. . It uses the same design-reuse and functional verification concepts like UVM, however is implemented in Python. In this webinar, we will introduce Cocotb, and will outline how Cocotb can provide significant savings in development time, promote code re-use and ultimately reduce project time-to-market and total development cost.  Play webinar   

Presenter: Sergei Zaychenko, Aldec Software Product Manager

Noise reduction is a key trend in currently available Clock Domain Crossing (CDC) Verification solutions. Most CDC tools on the market are unable to extract clocking and reset structures that match the original designer's intent. The designs often contain hundreds of vendor-specific blocks and 3rd-party IPs with unclear clock/reset relations. The timing of external interfaces might not be clearly defined, affecting the CDC results. Multiple clock modes, false paths and custom in-house synchronizers are not making CDC analysis any easier.

A user must typically go through several rounds of tool configuration, policy adjustments, clock/reset constraints refinements, description of timing intent for the black boxes. Bringing the focus to concrete configuration/constraint issues is challenging when forced to browse through thousands of violation messages and full schematics. Much time and effort might be lost on cleaning the configuration through printed CDC end-results, instead of keeping initial focus on correct control structures. In additional, an incorrect/incomplete configuration often leads to poor CDC tool performance.

In this webinar, learn how a seamless, phased-based CDC debugging methodology can reduce overall CDC signoff time.  Play webinar   

Abstract: The main purpose of DO-254 Verification Process (Chapter 6.2 of DO-254 Specification) is not merely to verify the functionality of the design but more importantly to obtain assurance that the hardware implementation meets the requirements defined in the early stages of DO-254 targeted project. It is absolutely critical to ensure that the same requirements are preserved in all stages of design and verification from planning to hardware testing. Learn in this webinar an effective approach to verifying your design from the RTL to hardware preserving the same requirements. Our experts will teach you how to use Assertions and Code Coverage for a systematic and comprehensive verification. Our experts will also demonstrate the advantages of component level verification with DO-254 CTS (Compliance Tool Set) ideal to hardware verification of Level A/B DO-254 designs. Play webinar   

Abstract: With the complexity of some FPGA designs now comparable to ASIC, designers are faced with challenging cost, power and functional goals. Leading-edge FPGA designs will now benefit from advanced verification methodologies, but do ASIC-focused EDA vendors offer the best solution? This webinar will explain how Aldec tools are uniquely positioned to efficiently support the verification of complex FPGA designs and how (in combination with the new devices from Lattice) designers can meet their functional, cost and power requirements for complex high volume applications. Play webinar   

Appendix B of RTCA DO-254 describes elemental analysis as one of the possible additional verification techniques for Level A and B complex electronic hardware. Code coverage in and of itself does not always satisfy the objectives of DO-254. This presentation provides background on elemental analysis and when code coverage is sufficient for HDL based designs. The discussion will cover the various types of code coverage and which ones are relevant to certification authorities. Suggestions for resolving coverage holes will also be discussed. Play webinar   

In this webinar, we’ll discuss typical synchronizer structures to put in place for CDC crossings as well as the most common mistakes in their structure. We’ll also cover some of the functional problems that often arise due to incorrect synchronization, as well as how to verify a project against CDC issues during the RTL design and RTL simulation design stages. Play webinar   

Writing code is easy. Reading code is hard. Maintaining code is hard. Writing "good" code is hard. So what's "good code"? Don't despair: the software engineering community has come up with tons of practical solutions! Now it's time to apply them to your next Python verification project with cocotb. In this talk, we'll look at best practices when writing cocotb test benches. Coding style, reviews, continuous integration, test, and code structure will all be discussed and applied to working with cocotb. A well-written cocotb test bench is sustainable: it will stay with you for many projects. This is your opportunity to learn how to get there. Play webinar   

As FPGA designs grow in size and complexity, the challenge of Clock Domain Crossing (CDC) verification becomes increasingly critical. Improper handling of asynchronous clock boundaries can lead to metastability, glitches, and loss of data coherency—causing unpredictable functional behavior in hardware. While AMD (Xilinx) Vivado Design Suite includes built-in CDC checks, its capabilities may be insufficient for complex, multi-asynchronous clock designs. Vivado's CDC reporting provides valuable insights, including Xilinx-specific checks such as the ASYNC_REG attribute, but lacks the depth of specialized CDC verification tools like ALINT-PRO. In this webinar, we will compare Vivado’s built-in CDC verification with the advanced capabilities of ALINT-PRO. Using real-world design examples, we will highlight CDC issues that Vivado may miss and demonstrate how ALINT-PRO enhances CDC analysis and debugging. Finally, we will showcase a case study on Ethernet MAC CDC verification, featuring multiple asynchronous clock domains. Play webinar   

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. In part 1 of this webinar series, we will show you how to verify a relatively simple DUT with low- to mid-quality requirements using a basic testbench without using any verification framework. We will also discuss the elements of a basic testbench infrastructure, show you examples of how to create self-checking testbenches with verbosity and alert control, and introduce the use of basic Bus Functional Models (BFMs) to speed up verification and debugging. Having shown you these basic testbench techniques, we will then introduce an open-source industry verification framework for VHDL designs called UVVM that you can use to verify a simple DUT. Play webinar   

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench - progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. In part 2 of this webinar series, we will show you how to verify a relatively simple DUT with high quality requirements using an advanced testbench without using any verification framework. We will also discuss the elements of an advanced testbench infrastructure to verify our simple DUT more efficiently, check and prove that we have indeed verified our simple DUT more thoroughly, start to use advanced Bus Functional Models (BFMs) that allow simpler and more advanced interface control, and introduce functional coverage. Having shown you these more advanced testbench techniques, we will continue to show how UVVM can be used to implement them in the simplest ways possible and with a focus on readability, maintainability, and extensibility. Play webinar   

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench – progressing from basic to advanced techniques. We will first use a simple DUT then go to a more complex DUT with simultaneous activities on multiple interfaces. In the concluding part of this webinar series, we are now ready to apply advanced verification to a complex DUT. From a verification point of view, one of the most error-prone characteristics of complex DUTs is the number of simultaneous activities on multiple interfaces. Unfortunately, there is very little awareness about the high risk this represents – not to mention all the late fixes required or, even worse, the escape of bugs into the customers’ products. In this webinar, we will explain some typical problem scenarios, how they are handled in most projects, and how they could be handled in a well-structured and advanced testbench – all independent of verification methodology. We will also describe how an advanced testbench can be simplified using generic testbench elements. Finally, we will show how such a testbench could be made using UVVM, and how this significantly improves overview, readability, maintainability, extensibility, debuggability, and reuse. Play webinar   

Abstract This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing, self-checking tests, messaging, reports, and Open Source VHDL Verification Methodology (OSVVM) helper utilities. The “transaction” in transaction-based testing is just a fancy word for an abstraction that represents a single action on an interface – such as a Send or Get on a streaming interface. We will look at alternatives in implementing transactions – including using OSVVM’s Model Independent Transaction library. Using transactions is important because they accelerate test case development, increase reuse, and reduce maintenance costs. Self-checking is essential in test cases as checking waveform output manually is time consuming, error prone, and soul-crushingly boring. Self-checking involves counting errors and using the count to create a pass/fail report when the test is completed. If we use signals (and there may be a collection, some of which might be in a different entity) we will need to sum them up and generate an error report. However, it is easy to forget one and give a false pass condition. OSVVM simplifies error counting and makes it reliable by creating a data structure in a package and using it to track the multitude of error sources. The pass/fail report is created by looking at the entire data structure for errors – so nothing is missed. We can even track and report separate sources of errors – such as different interfaces. Messaging (a.k.a. verbosity control) is about creating detailed informational messages when we are debugging and just pass/fail messages when running regressions. Since the messages may be generated by different entities, we need controls that have a wide scope. Furthermore, we may want to control different sources of messages independently. OSVVM simplifies the control of log messages (enable/disable) using the same data structure we use for tracking errors. Test reports are about quickly finding which tests in a suite of tests failed and why. OSVVM creates two levels of test reports. The OSVVM build summary report gives a summary of the pass/fail status of each separate test case that was run, and the OSVVM test case report provides details on the self-checking, functional coverage, and scoreboard/FIFO usage for each test case. When running sets of tests (such as during regression testing), these reports help us quickly find which test cases failed and why. The OSVVM helper utilities target simplifying testbench development with capabilities that include clock generation, reset generation and test case development with synchronization utilities such as WaitForClock and WaitForBarrier. About OSVVM OSVVM is a suite of libraries that allows any VHDL engineer to write VHDL testbenches and test cases for both simple unit/RTL level tests and complex, randomized full chip or system level tests. OSVVM is developed by VHDL experts who actively contribute to VHDL standards development to provide VHDL with verification capabilities that rival SystemVerilog + UVM. Getting your entire team united in using OSVVM will simplify deploying VHDL engineers to projects. Why VHDL for verification? According to the 2022 Wilson Research Group Functional Verification Study, in the FPGA market, 66% use VHDL for design, 58% use VHDL for verification, and 28% use OSVVM. Hence, VHDL is #1 for FPGA development and OSVVM is #1 for VHDL verification. Play webinar   

Abstract:
Aldec industry partner, ReneLife introduces its proprietary core technology, ReneGENE, for fast and accurate alignment of short reads obtained from the Next Generation Sequencing (NGS) pipeline. The technology, devoid of heuristics can precisely align the DNA reads against a reference genome at a single nucleotide resolution. As genomics permeates the entire landscape of biology, including biomedicine and therapeutics, ReneGENE creates a genomic highway that significantly contributes to reduce the time from sample to information without compromising on accuracy, critical for lifesaving medicare applications, biotechnology product development and forensics.

In this webinar, we present AccuRA, a high-performance reconfigurable FPGA accelerator engine for ReneGENE, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on a 8-core 3.5 GHz AMD FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments. AccuRA offers a need-based affordable solution, deployable both in the cloud and local platforms. AccuRA scales well on the Aldec platform, at multiple levels of design granularity.

Agenda:

• Introducing the world of genomic big data computing
• The need for accuracy and precision
• Introducing ReneGENE/AccuRA
• Product Demo
• Impact of ReneGENE-The Genomic Highway

Presenter: Santhi Natarajan, Ph. D (IISc) Play webinar   

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In part 1 of this webinar series, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally, we will talk about design verification of highly configurable design and IP blocks. Play webinar   

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In part 2 of this webinar series, we will show you important verification patterns providing solutions to repeatable randomization, error management and end-of-test checks. We will also provide an overview of how to define, develop and re-use verification components such as drivers, responders, and monitors. Then, we will talk about how to develop testbenches, and how to validate their correctness with reporting and statistics collection. We will provide code examples to illustrate the topics of discussion. Play webinar   

As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In this, the concluding episode of the webinar series, we will present advanced verification solutions for verifying complex design properties. We will talk about randomization, functional coverage, and the importance of code coverage to achieve overall design verification completeness. Also, we will provide an overview on other important topics such as assertion and transaction-based verification and debug, static design verification with linting tools and regressions support. Finally, we will talk about ‘Verification Done’, in terms of at what point can the verification be considered complete and how do we achieve it? Play webinar   

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency. The FPGA design architecture also affects several project and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness and verification/test workload.  Play webinar   

For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously. Play webinar