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Policy and Waiver configuration options that are available within the ALINT-PRO GUI can also be modified at the command line using specific "project.policy" and "project.waiver" commands. These commands can be configured and enabled quicker than making selections through the GUI, as are most other functionalities when it comes to using the command line.

XTrace allows users to detect and report unknown values (e.g. X, W, U, etc.) when they first appear, and before they are propagated through a design. Learn how to enable XTrace, set XTrace options, and view signals that contain unknown values.

The Accelerated Waveform Viewer is a high performance tool dedicated to reading and graphically presenting simulation data. Learn how to utilize advanced operations such as zooming, signal manipulations, cursors, measurements, bookmarks, browsing modes, and aliases.

Active-HDL’s Assertion Viewer allows the user to view two types of PSL and SystemVerilog objects during simulation: assert statements and cover statements. The viewer provides useful statistics about these objects in an easily accessible manner. This video provides an overview on how to access and use the Assertion Viewer window.

Active-HDL provides additional simulation modes, including one called Post Simulation Debug Mode. This advanced feature allows for viewing simulation results after the simulation has finished. Note that in this mode, some debugging tools normally available during simulation are not usable such as toggling breakpoints, using Dataflow, and stepping through code. Additionally, this feature does not check out the simulation features in your Active-HDL license, but instead checks out the Post Simulation Debug license feature. This video will go over how to access the mode, how to set up simulation settings to get post-simulation data, and what simulation and debugging tools are available in this mode.

Take a look on how to make use of the UVM Toolbox available in Riviera-PRO for debugging designs and making the most of your verification environment. Use the UVM Viewer, UVM Hierarchy, and UVM Configuration windows to represent UVM architecture and their TLM connections to improve the perspective of the architecture and dataflow. The UVM toolbox features are compatible with UVM 1.2, 1.1d and 1.0p1.

Code coverage is a useful source of metric, that analyzes code execution and can help us determine the completeness of the verification effort. It helps us identify corner cases that may not be executed in your design. Code Coverage analysis tools offered by Active-HDL can provide several different types of information related to the verification process of your design.

The UVM Register Generator is used to create Register Model files to incorporate into a UVM environment to use the Register Abstraction Layer of UVM. Automatically generating models for the RAL is particularly time saving, considering modern designs can consist of thousands of registers, and coding those by hand would be a long and tedious task, while still being a crucial aspect of the verification of the design. Using a CSV or IP-XACT register description, automatically generate a UVM register model, and quickly integrate it into your UVM environment for faster verification.

Active-HDL provides a number of coverage analysis tools to further enhance verification quality of HDL code. Coverage analysis uses ACDB (Aldec Coverage Database) as a unified format of storing different types of coverage data. This video will go into more detail on one of the Code Coverage options: FSM Coverage. FSM Coverage enables users to determine which states and transitions in the state machine diagram have been executed during simulation. To collect the FSM Coverage statistics, the HDL design code has to include SystemVerilog or Aldec proprietary pragmas indicating which constructs represent components of the state machine. The pragmas used in the HDL code are included in additional lines of comments and interpreted by the coverage engine. The FSM Coverage statistics can be stored in the Aldec Coverage Database (ACDB) files and presented in a textual or HTML report along with OSVVM Functional Coverage providing complete structural coverage and functional coverage with test results merging, ranking and analysis.

Due to the ability for tracking dependencies between design resources, makefiles can boost compilation efficiency in comparison to DO/Tcl macros. In Riviera-PRO, the makefile.tcl script is an auxiliary utility generating makefile configuration files intended for use with the Make software development tool that automates the compilation process for SystemVerilog/Verilog, VHDL, and EDIF files. This video goes over what’s needed to use the makefile.tcl and how to utilize the makefile.tcl script to compile a design within the Riviera-PRO environment.

Toggle Coverage measures design activity within terms of changes of signal logic values and creates a reports that states whether monitored signals were initialized, experienced rising and/or falling edges, and the number of rising/falling edges during a simulation session. Learn how to collect Toggle Coverage data and view the results in XML format.

Active-HDL provides a number of useful tools for state machines. Along with the FSM Editor, different types of testbenches can be generated from a state machine diagram using the FSM Testbench Generator. The code generated from the FSM diagram can also contain FSM Coverage. This video will demonstrate how to use the Testbench Generator and FSM Coverage together to get a comprehensive debugging experience for FSMs.

The Signal Agent is a Verilog task or VHDL procedure that allows for the monitoring and driving of signals from anywhere in the design hierarchy. This can be useful for mixed language designs during testbench development and design verification. This video will explain how the Signal Agent is used and demonstrate its use through a simple mixed language example design.

Ranging from RAMs to simple flip-flops, memory plays an important role in a variety of FPGA designs. Making it easier to debug their functionality, Active-HDL’s Memory Viewer allows for observing and changing the content of these memory objects during simulation. This video demonstrates debugging three common memory use cases (using VHDL) utilizing the Memory Viewer.

When you instantiate any Xilinx black box component in your design, Active-HDL will look for the vendor libraries to define functionality of the Xilinx Component. Before performing simulation of these designs, it is crucial not only to have the proper simulation libraries, but the correct version as well.

Linting can be ran directly from your design tool using the "Run In Aldec ALINT-PRO" feature available in Active-HDL. This feature can either generate a new tcl script that automatically converts the design workspace and performs linting or can use an existing script to perform after launching the ALINT-PRO software.

With Xilinx Vivado’s TCL store, integrating Active-HDL simulator in the Vivado work flow is easy. This combination allows users to extend Vivado’s rich synthesis and implementation tool set with Active-HDL’s high performance simulator. This seamless integration eliminates the need to manually map the source files between the two programs as this is all done in the backend.

Linting can be ran directly from your simulation tool using the "Check in Aldec ALINT-PRO" feature available in Riviera-PRO. This feature can either generate a new tcl script that automatically converts the design workspace and performs linting or can use an existing script to perform after launching the ALINT-PRO software.

Intel Quartus Prime Pro’s environment allows for the usage of 3rd party simulators through .tcl and .do scripts. Because of this, one can utilize Active HDL’s fast and comprehensive debugging and simulation environment. This video provides a general overview of how to simulate and debug with Active-HDL through Quartus Prime Pro using one of Quartus’ sample IP designs.

Complex hardware/software interactions within system-on-chip devices such as the Xilnx Zynq 7000 and others are requiring more advanced verification tools. Through co-simulation, programmable logic and processing systems can both be tested concurrently and early in the design cycle, allowing for hardware and software team members to work together and correct design bugs early in the verification process. Aldec's QEMU bridge, along with Aldec's Riviera-PRO, allows for this co-simulation, providing an interface between simulator and the QEMU machine emulator which can model the processing system of Zynq devices.