Name Products Type Action
6.1 License Installation Aldec Products (Nodelock and Floating)   
In order to properly use any Aldec software, Aldec provides customers with two types of licenses: node-locked and floating. This video will cover how to determine the license type as well as how to properly install each type of license onto a Windows machine.
Active-HDL, Riviera-PRO, ALINT-PRO, HES-DVM, DO-254/CTS Demonstration Videos
100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM Recorded Webinars
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating The Verification Of Hardware Dependent Software   
Software costs now dominate in SoC design. It is therefore imperative that the dependencies the hardware places on the software are captured and managed as early as possible. To ignore these is to risk project and budget overrun. In this webinar, we will illustrate why FPGAs are chosen as the verification platform for software integration. We will discuss the challenges of using FPGAs for verification and introduce the use of hybrid virtual prototypes. A comparison will be made between traditional FPGA ASIC prototypes and an FPGA-based emulation system. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating UVM Verification with Emulation   
In this video, Application Engineer Henry Chan, explains how emulation can help accelerate UVM-based testbenches and explores the benefits of emulation/acceleration over traditional simulation tools. A cursory overview of the Accellera SCE-MI standard as well as some necessary testbench modifications for emulation/acceleration are presented. A case-study using a UVM testbench and Network-on-Chip design is examined to demonstrate the benefits of emulation.
Riviera-PRO, HES-DVM Demonstration Videos
Aiding ASIC Design Partitioning for multi-FPGA Prototyping   
Whether it is an ASIC, ASSP or large FPGA design, emulation and prototyping are indispensable verification and validation activities. Often FPGA based platforms are chosen due to their scalability and versatility and more importantly, because of their runtime speed potential. What drives many away from this platform are the challenges of the multi-FPGA design setup that requires complex partitioning, arranging interconnections and managing multiple clock domains across multiple devices. Automation in this field is highly desirable to avoid time consuming and error prone hand-crafting and design hacks that would enable FPGA prototyping. Aldec HES™ Prototyping Platform and related solutions are here to mitigate these risks and facilitate rapid implementation of reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the HES-DVM tool that provides new partitioning utilities and can convert ASIC clocks to FPGA-proof structures. Awareness of clock domains and prototyping board connectivity resources facilitates in making wise decisions and allows achieving high clock ratios of FPGA prototypes. In this webinar, we will demonstrate the new HES-DVM prototyping flow that will increase your productivity in physical prototyping by shortening the setup time and increasing runtime speed of your design in FPGA.  Play webinar   
HES-DVM Recorded Webinars
FPGA Accelerator for Genome Aligner - ReneGENE   
Aldec industry partner, ReneLife introduces its proprietary core technology, ReneGENE, for fast and accurate alignment of short reads obtained from the Next Generation Sequencing (NGS) pipeline. The technology, devoid of heuristics can precisely align the DNA reads against a reference genome at a single nucleotide resolution. As genomics permeates the entire landscape of biology, including biomedicine and therapeutics, ReneGENE creates a genomic highway that significantly contributes to reduce the time from sample to information without compromising on accuracy, critical for lifesaving medicare applications, biotechnology product development and forensics.

In this webinar, we present AccuRA, a high-performance reconfigurable FPGA accelerator engine for ReneGENE, offered on Aldec HES-HPC™ for accurate, and ultra-fast big data mapping and alignment of DNA short-reads from the NGS platforms. AccuRA demonstrates a speedup of over ~ 1500+ x compared to standard heuristic aligners in the market like BFAST which was run on a 8-core 3.5 GHz AMD FX™ processor with a system memory of 16 GB. AccuRA employs a scalable and massively parallel computing and data pipeline, which achieves short read mapping in minimum deterministic time. It offers full alignment coverage of the genome (million to billion bases long), including repeat regions and multi-read alignments. AccuRA offers a need-based affordable solution, deployable both in the cloud and local platforms. AccuRA scales well on the Aldec platform, at multiple levels of design granularity.

  • Introducing the world of genomic big data computing
  • The need for accuracy and precision
  • Introducing ReneGENE/AccuRA
  • Product Demo
  • Impact of ReneGENE-The Genomic Highway
Presenter: Santhi Natarajan, Ph. D (IISc) Play webinar   
Riviera-PRO, HES-DVM, TySOM™ EDK Recorded Webinars
FPGA Design/Verification Best-Practices for Quality and Efficiency Part 1: FPGA Design Architecture Optimization   
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency. The FPGA design architecture also affects several project and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness and verification/test workload.  Play webinar   
Active-HDL, Riviera-PRO, ALINT-PRO, HES-DVM Recorded Webinars
FPGA Design/Verification Best-Practices for Quality and Efficiency Part 2: FPGA Verification Architecture Optimization with UVVM   
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously. Play webinar   
Active-HDL, Riviera-PRO, ALINT-PRO, HES-DVM Recorded Webinars
FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 3: Randomization – The Why, When, What & How    
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design, and as a result their products have significantly more undetected bugs. Randomization can be used in many ways, but it is of course also important to know when not to use it. This presentation will show several levels of applying randomization, both with respect to the actual DUT and the randomization functionality available. The main principles shown are tool independent, but the new UVVM randomization functionality will be used as examples, thus also giving you a kick start using this great tool. Play webinar   
Active-HDL, Riviera-PRO, ALINT-PRO, HES-DVM Recorded Webinars
FPGA Design/Verification Best-Practices for Quality and Efficiency

Part 4: Code, Functional and Specification Coverage   
Functional coverage is often mentioned together with constrained-random verification, and this is a great combination. However, functional coverage is also very useful even if you have no randomization at all. This is a great method for ensuring that you are in fact checking the right things in your testbench. Unfortunately, not many designers are applying functional coverage, and maybe part of the reason for that is the complexity surrounding previous solutions to this functionality. This presentation will show you how it works and how easy it is to get started with this new functionality in UVVM. The presentation will also explain and show the usage of Specification Coverage aka Requirement Coverage, which is a feature to track that all your specification requirements have been covered. Many of us are already familiar with Code Coverage since it’s very easy to use, but some important issues will be presented. Play webinar   
Active-HDL, Riviera-PRO, ALINT-PRO, HES-DVM Recorded Webinars
FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond   
As today's SoC and ASIC designs evolve to integrate the latest embedded processors, media interfaces, and high-speed serial communication, FPGA prototyping platforms are struggling to maintain the pace of designs surpassing the 100 million ASIC gate count. With the evolution of modular architectures and robust scalable backplanes, FPGA prototyping vendor solutions such as Aldec HES-7™ are able to keep pace with hardware designers. The HES-7 backplane enables scaling up to 96M ASIC gates, which can be serially daisy-chained for designs which require additional capacity. Play webinar   
HES-DVM, HES-7 Recorded Webinars
FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms   
Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically referred to as ASIC FPGA prototyping. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of these systems. In this webinar we will introduce an approach where UVM tests can be accelerated with the use of an FPGA co-emulator. The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate. This enables tests to be moved seamlessly from simulation to the accelerator and back again. Play webinar   
HES-DVM, HES-7 Recorded Webinars
HES™ Overview: A Hybrid Verification and Validation Platform   
Aldec Hardware Emulation Solutions is a hybrid verification and validation ecosystem for hardware and software teams developing the latest SoC and ASIC designs. Partnering the latest high-capacity FPGA technology with industry leading co-emulation standards, HES allows for multiple modes of verification and validation including bit-level simulation acceleration, transaction-level emulation, Hardware prototyping, and Virtual Modeling.
HES-DVM Demonstration Videos
HW / SW Co-Verification: Why wait for silicon?   
Abstract: Traditional design flows postpone HW/SW integration and co-verification until the ASIC prototype is ready. With constantly shrinking time-to-market requirement this is significantly too late. If some HW bugs are identified during SW integration phase then it is impossible to make HW changes. Designers have to find sophisticated SW workarounds in order to avoid costly re-spins. Learn from Aldec how to start HW/SW integration and co-verification much earlier in your design flow along with the extensive debugging capabilities on both sides of HW and SW. Find out how to enable HW and SW design teams collaborate on a whole new level that has never been done before. Play webinar   
HES-DVM Recorded Webinars
How to Build PCIe Speed Adapters for In-Circuit SoC Emulation   
Hardware assisted verification became much more affordable due to the availability of high capacity FPGAs such as Xilinx Virtex UltraScale US440 and their adoption for emulation verification environments. One of the advantages of FPGA-based emulation systems is that it’s much more flexible than traditional processor-based systems when it comes to connecting external peripherals. In this presentation we will demonstrate how to take advantage of the FPGA platform to build the PCI Express speed adapter and connect the emulated SoC design with the external PCIe-based Network Interface Card that runs at its target speed and provides connection of the SoC to the real LAN network traffic.  Play webinar   
HES-DVM Recorded Webinars
Hybrid SoC Verification and Validation Platform for Hardware and Software Teams   
Hardware and Software teams both play a key role in developing the latest SoC and ASIC designs. Early access to hardware allows both teams to work concurrently with one another, increasing overall throughput and enabling hw/sw co-design and co-verification. Utilizing the latest in FPGA Technology with Aldec's Hardware Emulation Solutions, designers have a complete verification and validation tool capable of simulation acceleration, transaction-level emulation, and hardware prototyping. Utilizing the latest in co-emulation standards, HES-DVM™ allows designers to integrate virtual platforms and real time interfaces via speed adapters to provide a high-speed hardware emulation environment. Play webinar   
HES-DVM, HES-7 Recorded Webinars
New Mirror-Box Technology for Hardware-Assisted Simulation   
Aldec adds new and innovative debugging technologies to HES platform for Simulation Acceleration, providing verification engineers capabilities to quickly verify RTL designs with longer test cases and obtain faster results. Learn Aldec's new debugging technologies including Mirror-Box, ideal for quick smoke-tests runs where you can modify your HDL code and run simulation in the FPGA hardware without rerunning Synthesis and Place and Route. Obtain simulation speed up factor of 10-100X with accelerated debugging to detect more errors and bugs per day, ultimately helping you meet tight time-to-market deadlines. Play webinar   
HES-DVM Recorded Webinars
Partitioning Design for Custom or In-house Designed Multi-FPGA Board   
Presently, emulation and prototyping are essential verification and validation techniques for a SoC, ASIC, ASSP or large scale FPGA design. The FPGA based prototyping platforms are superior due to their performance and versatile connectivity. However, challenges of the multi-FPGA design setup requiring complex partitioning, I/O interconnections and mapping multiple clock domains across multiple devices drive many away from this platform. Design partitioning assistant software that can be used with either off-the-shelf or even custom made FPGA boards can significantly reduce the risk and time of the prototype bring-up. Aldec HES-DVM™ Prototyping Platform is here to aid in rapid implementation of fast and reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the DVM tool that provides partitioning utilities and can convert ASIC clocks to FPGA-proof structures, automate I/O assignment and control the timing critical paths across the board. We will demonstrate the HES-DVM prototyping flow that can be used with custom or in-house designed boards, even before the FPGA board design is finished. The results of preliminary partitioning can provide invaluable feedback to the board design team and a handful of hints on design-specific board improvements.  Play webinar   
HES-DVM, HES™ Boards Recorded Webinars
QEMU Co-emulation with FPGA    
The FPGA or ASIC SoC require a robust pre-silicon hardware/software co-verification platform. Virtual platforms are used successfully as high-speed simulation vehicle but only for standard components like CPU, memory, timers and the like. The challenge emerges when custom IP-core is added to the design. Developing device drivers using HDL simulation is counterproductive and testing operating system and application stack is impossible. Hybrid co-emulation of standard machine virtualizer with FPGA bridges the gap in verification environment. QEMU is a generic and open source machine emulator that supports various computer hardware architectures including Intel x86 and ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a hybrid co-emulation environment for SoC designs. We will demonstrate the latest QEMU Bridge designed to provide connection between CPU subsystem in QEMU and custom hardware IP-Core run in the HES FPGA board and mapped as PCI Express device in QEMU. We will also show how software stack GDB debugger can be used in step-lock mode with the Aldec Hardware Debugger to provide full and deterministic view of the entire SoC.  Play webinar   
HES-DVM Recorded Webinars
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