Play Webinar

Title: Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

Description: Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of the multi-FPGA design setup like partitioning, multiplexing limited I/O interconnections and mapping multiple clock domains across multiple devices may cause significant delays in prototype bring-up and verification schedule. Design partitioning tool that can be used with either off-the-shelf or custom made FPGA boards will automate the most tedious tasks and so significantly reduce the risk. Aldec provides HES-DVM Proto toolbox with automatic design partitioning for multiple FPGAs including Xilinx Virtex-7 and UltraScale XCVU440. In this webinar we will demonstrate how to compile and partition an open source design of Deep Learning Accelerator into 6 FPGAs in 6 steps which are fully automated.


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