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Fast Track to Riviera-PRO, Part 2: Advanced Debugging, Code Coverage and Scripting   
Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.  This second webinar of a two-part “Fast Track” series is designed to help functional verification engineers get up to speed quickly. In this webinar, you’ll learn about more debugging tips and we’ll also cover Tracing Logic and how to run code coverage in Riviera-PRO. We’ll also take a look at Plots - a new way of analyzing results.  Play webinar   
Riviera-PRO Recorded Webinars
100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM Recorded Webinars
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating The Verification Of Hardware Dependent Software   
Software costs now dominate in SoC design. It is therefore imperative that the dependencies the hardware places on the software are captured and managed as early as possible. To ignore these is to risk project and budget overrun. In this webinar, we will illustrate why FPGAs are chosen as the verification platform for software integration. We will discuss the challenges of using FPGAs for verification and introduce the use of hybrid virtual prototypes. A comparison will be made between traditional FPGA ASIC prototypes and an FPGA-based emulation system. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Addressing the Challenges of SoC Verification in practice using Co-Simulation   
Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing systems (PS) with state of the art programmable logic (PL). This combination allows system to be architected to provide an optimal solution. Verifying this interaction between the PS and PL presents a challenge to the design team. While each can be verified in isolation using QEMU for the PS and Riviera-PRO for the PL. The integration between the PS and PL all too often takes place late in the design cycle when the impact of addressing issues raised is larger in both time and cost. There is however, another way which is Co-Simulation, which can be performed early in the development cycle. This webinar will explore the challenges which are faced by SoC users, introduce the concept of Co-Simulation and its constituent parts along with demonstrating advanced debugging techniques. We will examine the required environment and pre-requisites needed to perform Co-Simulation. Detailed examples will then be presented to demonstrate basic and advanced debugging concepts. Based upon a Zynq implementing a Pulse Width Modulation IP core operating under SW control. We will look at examples which introduce basic Co-Simulation flow like waveform inspection along with advanced debugging aspects such as software and Hardware breakpoints and single stepping. These techniques will enable us to identify and debug issues which reside in both the software and hardware design. Co-Simulation enables you to develop your application faster and reduce the bring up time once the application hardware arrives for integration. This webinar will demonstrate these benefits and more which are gained when Co-Simulation is used, while demonstrating the ease with which the environment can be established and simulation performed. Play webinar   
Riviera-PRO, TySOM Boards Recorded Webinars
Advanced RTL Debugging for Zynq SoC Designs   
Presenter: Radek Nawrot, Aldec Software Product Manager

Abstract: Designers of complex embedded applications based on Xilinx® Zynq™ device require a high-performance RTL simulation and debugging platform. In this webinar, you will learn several advanced RTL debugging methodologies and techniques that you can employ for your block-level and system level simulation. You will learn how to use Dataflow, Code Coverage, Xtrace and Waveform Contributors for analyzing the errors in your AXI-based Zynq designs.

We welcome you to refer to the following Application Notes prior to the webinar:
Xilinx AXI-Based IP Overview
Simulating AXI BFM Examples Available in Xilinx CORE Generator
Simulating AXI-based Designs in Riviera-PRO
Performing Functional Simulation of Xilinx Zynq BFM in Riviera-PRO

Agenda
  • Embedded development flow between Xilinx Vivado™, SDK™, Riviera-PRO™ and TySOM™
  • Quick introduction to AXI
  • Running Riviera-PRO from Vivado
  • Code Coverage in simulation process
  • Advance dataflow- design overview
  • Bug injection – Xtrace in action
  • Waveform with Contributors – seek bug in code
 Play webinar   
Riviera-PRO, TySOM™ EDK Recorded Webinars
Aiding ASIC Design Partitioning for multi-FPGA Prototyping   
Whether it is an ASIC, ASSP or large FPGA design, emulation and prototyping are indispensable verification and validation activities. Often FPGA based platforms are chosen due to their scalability and versatility and more importantly, because of their runtime speed potential. What drives many away from this platform are the challenges of the multi-FPGA design setup that requires complex partitioning, arranging interconnections and managing multiple clock domains across multiple devices. Automation in this field is highly desirable to avoid time consuming and error prone hand-crafting and design hacks that would enable FPGA prototyping. Aldec HES™ Prototyping Platform and related solutions are here to mitigate these risks and facilitate rapid implementation of reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the HES-DVM tool that provides new partitioning utilities and can convert ASIC clocks to FPGA-proof structures. Awareness of clock domains and prototyping board connectivity resources facilitates in making wise decisions and allows achieving high clock ratios of FPGA prototypes. In this webinar, we will demonstrate the new HES-DVM prototyping flow that will increase your productivity in physical prototyping by shortening the setup time and increasing runtime speed of your design in FPGA.  Play webinar   
HES-DVM Recorded Webinars
Aldec and SynthWorks: OS-VVM: Open Source - VHDL Verification Methodology   
Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
ARM Cortex SoC Prototyping Platform for Industrial Applications   
Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms allow designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this webinar, we demonstrate how to tackle industrial design applications with Aldec’s HES-7™, which supports ARM® Cortex™-A9 based designs by leveraging Xilinx® Zynq® All Programmable SoC. Play webinar   
HES-7 Recorded Webinars
ASIC/SoC Prototyping with Aldec’s new HES-7 Board   
Aldec's newly released FPGA-based prototyping platform, HES-7™, leverages Xilinx® Virtex®-7 FPGA. Xilinx has introduced a new Stacked Silicon Interconnect technology (SSI), enabling a single Virtex-7 to have 2M logic cells, making it the industry’s largest capacity FPGA. This webinar will provide an overview of modifications to previous Xilinx architecture and the structuring of SSI technology. The webinar will also present how the Virtex-7 benefits FPGA-based prototyping platforms, and will also provide an overview of HES-7 key features. Play webinar   
HES-7 Recorded Webinars
Assertions - A Practical Introduction for HDL Designers   
The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Benefits of Requirements Management for Safety-Critical FPGA Projects   
Requirements are the source of all design and verification activities in a project lifecycle for safety-critical applications. But requirements often change during design and verification and can introduce unintended errors late in the project. If requirements are not managed efficiently, projects get delayed and in some cases fail. In this webinar, we will introduce the concepts of Requirements Management and how to enable it in your organization to increase product quality, save time and cost and help meet safety-critical standards. Play webinar   
Spec-TRACER Recorded Webinars
Best Design Practices for High-Capacity FPGA Devices   
With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this presentation, we will focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues. Play webinar   
ALINT Recorded Webinars
Best Practices for DO-254 Requirements Traceability   
DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. Learn in this webinar traceability best-practices for design assurance level (DAL) A FPGAs. We will provide insights to questions such as: What is the recommended approach when tracing from FPGA requirements to HDL design sources, implementation, test cases and testbench and test results? What type of output files are needed for traceability? What certification authorities look for when they review the traceability data? Play webinar   
Spec-TRACER, DO-254/CTS Recorded Webinars
Better Coverage in VHDL   
Abstract: Experienced users of VHDL simulation with testbenches appreciate additional layer of safety that Coverage Analysis gives them. But are all kinds of coverage equally beneficial? While Code Coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar we will show how to improve quality of the design using Property Coverage and Functional Coverage (with help of OS-VVM). Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Closed Loop Verification of Large Designs   
Abstract: Modern digital designs reached sizes so huge that traditional, simplistic verification no longer works. Large number of design sources, multiple teams and tools using them, almost infinite stream of results they produce - all those factors create new management challenges. Our webinar will show how verification planning, simulation and regression management can be easily handled using Agnisys and Aldec tools.  Play webinar   
Riviera-PRO Recorded Webinars
Decrypting Encryption in HDL Design and Verification   
Abstract: The issue of securing information flow was very important in the past (mainly in diplomacy and military applications) and became even more important recently, with new applications such as banking (ATM transactions), on-line commerce (e-store transactions), media (pay-per-view contents) and hardware design (secure IP delivery). All those applications face one common problem nicely described in the old joke: the only truly secure information is the one that cannot be read by anybody. Both hardware designers and tool designers must find the balance between security and usability, which can be achieved only by implementing well tested algorithms and workflow. Using Aldec implementation of Secure IP Delivery as the vehicle, this presentation provides informative overview of recommended ciphers and methodologies that can be used by a wide, technical audience.  Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
DO-254 - How to Increase Verification Coverage by Test (Aldec and Altera)   
As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements describing FPGA I/Os must be verified by test. The problem is that testing the FPGA device at the board level provides very low FPGA I/O controllability and visibility, therefore, giving you the inability to verify specific requirements by test. In this webinar, Aldec will demonstrate how you can verify all FPGA level requirements by test. All of the requirements verified during simulation can be repeated and verified in the target device. We will demonstrate a unique solution that enables requirements-based test by reusing the testbench as test vectors for testing the device at-speed. In this webinar, Altera will also share insights into the market trends observed from different applications and discuss some of the solution strategies that will address the system reliability concerns. Play webinar   
DO-254/CTS Recorded Webinars
DO-254 FPGA Level In-Target Testing   
Functional verification of digital designs in real hardware has been a serious undertaking when developing under DO-254 standard. Section 6.2 Verification Process of RTCA/DO-254 specifies that requirements must be preserved and verified from RTL simulation stage to hardware verification stage. Learn in this webinar examples of common challenges that are usually encountered during hardware verification, and more importantly, the solution to overcome these challenges. This webinar will highlight a unique methodology to replay RTL simulation in the target device at-speed that can significantly reduce the verification cycle. Play webinar   
DO-254/CTS Recorded Webinars
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