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Accelerate SoC Simulation Time of Newer Generation FPGAs   
Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM White Papers
Debugging SCE-MI Co-Emulation in Riviera-PRO   
Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.
Riviera-PRO, HES-DVM White Papers
Designing UVM Testbench for Simulation and Emulation of Network-on-Chip Design   
Universal Verification Methodology (UVM) is one of the most popular approaches in using transactional testbench environment. The growth of SoC designs forces design and verification teams to use emulation as a way to speed-up verification process. Standard CoEmulation Modeling Interface (SCE-MI) provides ways to connect emulated design with transactional testbench. This paper describes how to use SCE-MI to create UVM test environment that is ready for both simulation and emulation.
HES-DVM White Papers
Meeting Growing Verification Demands   
Abstract: The first decade of the 21st century brought tremendous growth of the size of typical digital design, triggering growing demands for faster, safer and more thorough verification. In response to those demands, many new flavors of verification were invented and implemented in the tools, making engineers face difficult choices. This paper gives detailed overview of currently available verification methodologies suitable for large designs and shows how Aldec tools can help in their implementation.
Riviera-PRO, ALINT, HES-DVM, HES-7 White Papers
Partitioning Challenges in Multi-FPGA Prototyping   
Multi-FPGA prototyping of ASIC & SoC designs enables the highest clock rates among emulation techniques. However, design setup for prototyping is much more complicated and challenging. In this White Paper we uncover the common challenges of partitioning design to multiple FPGAs and provide solutions that will improve your prototype quality and shorten time spent on design setup.
HES-DVM, HES™ FPGA Boards White Papers
SCE-MI obviously. But which one?   
About three SCE-MI 2 use models: macro-, function- and pipes-based. Differences, use cases and recommendations.
HES-DVM, HES-7 White Papers
Simulation Acceleration with HES XCELL   
Abstract: Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform.
HES-DVM, HES-7 White Papers
SoC verification made easy with Aldec HES-DVM   
As designs grow larger, the time spent verifying a project is growing longer as well. As a solution, some companies are trying to ‘shift-left’ their schedules. Verification via software simulators is not fast enough for large System-on-Chip (SoC) design projects, therefore one option is to use an FPGA emulator to speed up the design process. But what happens when a bug occurs? This document describes Aldec® HES-DVM™ features that can help speed up debug and verification of the SoC, in order to achieve faster time-to-market.
HES-DVM White Papers
Verification of Ethernet Designs with SCE-MI based Aldec Emulator   
Abstract: This white paper presents how to use modern verification techniques for advanced ASIC and SoC designs. Network based application has been selected for this study as a real life design project. Verification process will be performed using Aldec hardware emulation system called HES with transaction based SCE-MI interface used for testing activities. The key objective is to perform the verification of the Ethernet Network Switch with real data delivered directly from Ethernet network in very limited time assigned for verification setup process.
HES-DVM, HES-7 White Papers
Virtual Modeling with Aldec and Imperas   
Abstract: Virtual platforms play a significant role in system level development, but they require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP™ (Open Virtual Platforms) and OVPsim™ (OVP simulator). Hardware and Software design teams are now able to simulate and debug virtual models of processors, memories and peripherals while the rest of the system resides in the emulator board running at MHz clock speeds.
HES-DVM, HES-7 White Papers
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