Why are the JTAG interfaces for Spartan-6 and big 7-series FPGA chips separated?


The JTAG interface is divided into 2 chains to prevent accidental/unintended reconfiguration of the Spartan-6 FPGA chip, which controls processes of programming, testing, clock module configuration, etc.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.