VHDL Compilation Standards

Description

I run into following compilation errors:

# Error: COMP96_0104: filename.vhd: Undefined type of expression.

# Error: COMP96_0077: filename.vhd: Assignment target incompatible with right side. Expected type 'STD_ULOGIC_VECTOR'>.

If we run compilation using acom -2008 or -2006 option COMP96_0071, COMP96_0104 and COMP96_0077 errors are detected. Meanwhile if we use acom -2002 option no warning is detected. Is it correct behavior based on VHDL 2008 standard?

Solution

There are some changes between version 2002 and 2008 regarding STD_LOGIC_VECTOR type declaration and STD_LOGIC_UNSIGNED package. Most of STD_LOGIC_UNSIGNED package has been moved to the NUMERIC_STD_UNSIGNED one.

Please simply comment previous and add NUMERIC_STD_UNSIGNED in the code:

Example:
--use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD_UNSIGNED.all;

For more information about migration please refer to VHDL 2008 Migration Tips chapter/section in our Help.



Printed version of site: www.aldec.com/en/support/resources/documentation/faq/1183