Unknown VHDL Compilation Error with Daggen


I received the following error message when I was trying to compile a VHDL file. What I can do to fix it?

Error: DAGGEN_0007: <file name.vhd : Error during conversion >


Please try the following:

  • 1. Open your design

  • 2. Right-click working library in Design Browser and select “Delete simulation data” from the drop down menu.

  • 3. Compile the file again.

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