Unknown VHDL Compilation Error with Daggen

Description:

I received the following error message when I was trying to compile a VHDL file. What I can do to fix it?

Error: DAGGEN_0007: <file name.vhd : Error during conversion >

Solution:

Please try the following:

• 1. Open your design

• 2. Right-click working library in Design Browser and select “Delete simulation data” from the drop down menu.

• 3. Compile the file again.