How to check detailed Simulation Delay File (SDF) annotation report when doing the timing simulation?


SDF files are produced by implementation tools and contain delay data and timing checks. Active-HDL supports the latest version of SDF.

In VHDL designs, data from SDF file can be loaded by passing the appropriate arguments to the asim command when simulation is initialized. You can also specify SDF files by using the Design Settings dialog box.

In Verilog designs, SDF data is typically loaded by the $sdf_annotate task placed in Verilog code. Specifying the SDF file with the asim command (or with the GUI) is also possible.

Active-HDL loads SDF data when simulation is initialized (not when you start running the simulation with the run command).

SDF error limit specifies that all SDF errors should be reported to the Console window. If omitted, only the first 100 errors are printed and then the total number of errors is reported.

For more information go to Help | Index | SDF Annotation

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