How do I stop the simulation when a VHDL assert statement fails?

Description

I'd like my simulation to break when an error is thrown so that I can investigate it and see what is going on.

VHDL code example:

assert (data = check)
report "ERROR: Data readback not as expected."
severity error;

Solution

Active-HDL

Set the value of the breakassertlevel variable to 2 by passing the command displayed below to the Console. Alternatively, define the assertion severity level by using the Break on assertion option available in the Simulation category of the Preferences dialog box.

set breakassertlevel 2

By default, this variable is set to 3 which sets the minimum severity level to failure. When 2 is set, the variable stops the simulation when an assertion with the error severity level occurs and then you can resume the simulation from that point on. In turn, when breakassertlevel is set to 1, the simulation will be stopped when an assertion with the warning severity level is encountered. Therefore, when the default value is used, the simulation continues after the error message.

Riviera-PRO

Pass the vhdlassert.break command with the error argument to the Console as it is presented below. Alternatively, define the assertion severity level by using the Break on VHDL assertion option available in the Simulation | VHDL | Assertions category of the Preferences dialog box. By default, the severity level is set to failure.

vhdlassert.break error

Except for passing the error argument that breaks the simulation when an assertion with the error severity level occurs, the simulation can be also stopped when the failure or warning argument is used causing the simulation to break when the assertion with the failure or warning severity level is encountered.

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