Does the Aldec simulator have hierarchical referencing similar to ModelSim's Signal Spy?


I would like to set a probe in my testbench to monitor a signal inside of the unit under test. How can I make a hierarchical reference to it?


We have similar feature named "Signal Agent". Basically you use Aldec's provided functions to map signals across hierarchical levels:


signal_agent (<source>, <destination>, <verbose>)

Refer to the Active-HDL documentation (as shown below) for more details on using signal_agent command:

  1. Click on the Help tab.

  2. Select either PDF Documentation or HTML Documentation.

  3. Then, select either option:

    • For Verilog: click on Using Active-HDL | Compilation | Verilog Compilation | Signal Agent

    • For VHDL: click on Using Active-HDL | Compilation | VHDL Compilation | Utility Routines | Signal Agent

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.