Does the Aldec simulator have hierarchical referencing similar to ModelSim's Signal Spy?

Description

I would like to set a probe in my testbench to monitor a signal inside of the unit under test. How can I make a hierarchical reference to it?

Solution

We have similar feature named "Signal Agent". Basically you use Aldec's provided functions to map signals across hierarchical levels:

Example:

signal_agent (<source>, <destination>, <verbose>)

Refer to the Active-HDL documentation (as shown below) for more details on using signal_agent command:

1. Click on the Help tab.

2. Select either PDF Documentation or HTML Documentation.

3. Then, select either option:

   • For Verilog: click on Using Active-HDL | Compilation | Verilog Compilation | Signal Agent

   • For VHDL: click on Using Active-HDL | Compilation | VHDL Compilation | Utility Routines | Signal Agent