Concatenation in VHDL


I received the following error message when I was trying to compile a VHDL file. What can I do to fix it?

Error: COMP96_0547: <File Name>.vhd : Choice in selected signal assignments and case statements must be locally static. Use -relax to allow nonstatic expressions and discrete ranges.


The concatenation operator usage with what you are trying to do has been approved and implemented for VHDL 2008 standard by IEEE commitee.

Please use the VHDL 2008 standard when you compile the code either by going to Design | Settings | Compilation | VHDL or by adding acom -2008 in the script.

If you want to use a previous VHDL version, please use the mentioned -relax switch for the acom command or set this switch in Design | Settings | Compilation | VHDL | Relax LRM requirements.

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