Starting Active-HDL as the Default Simulator in Xilinx ISE

Introduction

This document describes how to start Active-HDL simulator from Xilinx ISE Project Navigator to run behavioral and timing simulations. This application note has been verified on Active-HDL 9.1 and Xilinx ISE 13.4. This interface allows users to run mixed VHDL, Verilog and System Verilog (design ) simulation using Active-HDL as a default simulator.

Installing Xilinx libraries in Active-HDL

In order to run the simulation successfully, depending on the design both VHDL and Verilog libraries for Xilinx may have to be installed in Active-HDL. You can check what libraries are currently installed in your Active-HDL using Library Manager tool. You can access the Library Manager from the menu View>Library Manger>.

You can install precompiled libraries in multiple ways:

  1. If you are using Active-HDL DVD to install the software, during the installation, you will get the option to select and install the Xilinx libraries

  2. If you have received a web link to download Active-HDL, on the same page you will find the links to download Xilinx libraries.

  3. At any time you can visit the update center to download the latest Xilinx libraries at http://www.aldec.com/support

Set Active-HDL as Simulator in Xilinx Project Navigator

After creating a project, open your Xilinx project in ISE Project Navigator. Now we will have to replace the link to Model Tech simulator with the Active-HDL executable file. To do that open Preferences window in Project Navigator (use menu Edit | Preferences). In the Preferences window, go to the Integrated Tools section under ISE General category. Point to the Xilinx ISE .bat file (C:\Program File\Aldec\Active-HDL X.X\BIN\xilinx_ise.bat) in the Model Tech Simulator box as shown below.

Figure 1 Setting up the executable for Active-HDL

Click Open and then OK to close the Preferences window.

Setting Simulator Properties in Xilinx Project Navigator

After setting up Active-HDL as a simulator, you need to set up the simulator properties. In the Project menu, go to Design Properties and set the Simulator setting to Modelsim-SE Mixed.

Figure 2 Setting the Simulator to Modelsim-SE Mixed

After that you should be able to see the ModelSim Simulator command in the Processes tab as shown below.

Figure 3 Selecting Simulation Property

Now right-click on Simulate Behavioral Model and select the Process Properties option from the context menu. In the Process Properties window select Simulation Properties.

  • Change the Compiled Library Directory to point to Vlib within the Active-HDL installation.

    NOTE: For users who are using Active-HDL 9.3 or later will need to change the directory as follows:

    • VHDL: C:\Aldec\Active-HDL<ver>\vlib\xilinx_ise\vhdl

    • Verilog: C:\Aldec\Active-HDL<ver>\vlib\xilinx_ise\verilog

  • In the Other VSIM Command Line Options field, add +access+r. This enables the access to add signals to the waveform viewer.

Figure 4 Setting up the display property

Under the Display Properties. Make sure all the options are unchecked as shown below in the figure 5.

Figure 5 Setting up the display property

Starting Active-HDL from Xilinx ISE

To start Active-HDL simulator, right-click on Simulate Behavioral Model in the Processes tab and select Run. Active-HDL will be started. The source and script files will be added to the created design, compiled, and simulated.

Figure 6 Simulation launched in Active-HDL

To Run A Timing simulation

To run a timing simulation, switch the design view to Implementation.

Figure 7 Design View: Implementation

  • Run the synthesis and implementation process by pressing the Implement Top Module button or by right-clicking the top-level module and selecting Implement Top Module.

    Figure 8 Run Synthesis and Implementation Process

  • Expand Implement Design and run the Generate Post-Place & Route Simulation Model process.

    Figure 9 Generate Post-Place & Route Simulation Model

  • Switch the design view to Simulation and change the drop down box from Behavioral to Post Route.

    Figure 10 Post Route Simulation

  • Right-click on Simulate Post-Place & Route Model in the processes window and select Process Properties.

  • You can observe the additional field Delay Values To Be Read from SDF, this indicates an SDF was created to run a timing simulation.

    Figure 11 Process Properties for Timing Simulation

  • The Display Properties should remain the same as the previous simulation.

  • Under Simulation Model Properties you can also observe the -sdf switches used for the timing simulation.

    Figure 12 Simulation Model Properties

  • Run the simulation by right-clicking on Simulate Post-Place & Route Model and select run.

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