Getting Started with Active-HDL Batch Mode

Running Active-HDL in the Tool Shell Mode

You can start Active-HDL in the shell mode by running vsimsa.bat file located in Active-HDL installation directory. The vsimsa.bat file is a wrapper script for the bin\vsimsa.exe batch mode simulator.

Note: All paths in this document are relevant to the installation directory of Active-HDL.

When vsimsa shell starts, you can start manually entering Active-HDL commands in the command prompt as shown below.

# creating library
$ alib work
# ALIB: Library `work' attached.
# work = c:\my_designs\fpc_pll\work\work.lib
# setting work library as the default target for all commands
$ set worklib work
# VSIMSA: 'work' is now working library.

Note: `$ indicates vsimsa shell prompt

Alternatively you can put Active-HDL commands in the macro file with .do or .tcl extension and execute them in the batch:

$ do runsim.do

where runsim.do macro script can contain the following commands:

# creating library
alib work
# setting work library as the default target for all commands
set worklib work
# compiling verilog source files
acom fpc.vhd fpcTB.vhd
# starting simulation with tb_top as the top level module
asim fpc_tb
# running the simulation
run 1000us
# closing the simulation
endsim
quit

Note: For Verilog compilation you have to use alog command

alog file1.v file2.v

For complete syntax of the above Active-HDL commands, please refer to the on-line help within Active-HDL, or simply type "help <command_name>" in the command console, i.e. "help vsimsa", "help acom", "help asim", etc.

You can also pass the macro file as an argument when you start vsimsa from the DOS shell and create a log file with a .bat file containing the following lines of code:

vsimsa -do runsim.do > mylog.log
exit

The vsimsa command prompt will return when the execution of the vsimsa with macro is completed without errors. If you want the vsimsa shell to be closed upon the script completion end your macro script with the quit command. If the macro execution errors out, vsimsa will drop to the tool shell enabling you to read all the messages and examine the source of the problem. If you want vsimsa to continue macro execution after it reports an error, add the following entry to your macro file:

$ onerror {resume}

Running Active-HDL Commands in the OS shell

The most important Active-HDL commands are available as standalone executables and can be invoked directly from the operating system shell. All external commands are located in the bin/ subdirectory of the Active-HDL installation directory. External commands can be used for library management, compilation, simulation, etc.

Below you can find the list of most frequently used Active-HDL commands. For complete syntax of the above Active-HDL commands please refer to the product help within Active-HDL, or simply type "help <command_name>" in the command console, i.e. "help vlib", "help vlog", "help asdb2vcd", etc.

Library Management Commands

  • vlib (creates a new library)

  • vlist (lists libraries visible from the current directory)

  • vdir (lists library contents)

  • vdel (removes compiled units from a library)

  • vmap (adds or removes library mappings)

Compilation Commands

  • vcom (compiles VHDL files)

  • vlog (compiles Verilog files)

  • ccomp (compiles SystemC files)

  • addsc (imports SystemC modules from a shared object library or a dynamic-link library)

Simulation Commands

  • vsim (elaborates the design and runs simulation)

ASDB Manipulation

  • Type "help" at the "$" prompt from within the vsimsa shell to obtain more information on the available commands that can be used.

  • asdbcompare (compares two ASDB files and generates a text report)

  • asdb conversion utilities (asdb2ctf, asdb2ctv, asdb2lst, asdb2macro, asdb2vcd, vcd2asdb)

Below you can see a complete example of the shell script that calls external Active-HDL commands to compile and simulate the design.

# create library v_bjack
vlib v_bjack
# compile source files
# working library is specified with –work switch
vlog -work v_bjack c:/my_designs/samples_83/v_bjack/src/*.v
# initialize simulation
vsim  -c -lib v_bjack V_BJACK_tb
run -all
endsim

Note: that you have to use -c switch with the external vsim command to run the simulation in the batch (console) mode. Omitting -c switch will run the simulation in the GUI mode.

Please refer to the Waveform section below to see how to enable signal values dumping in Active-HDL.

Signal Waveforms

Active-HDL stores simulation results in "wave.asdb", which is the default value for $waveformoutput, and may be changed with the set command from vsimsa shell.

  • Aldec simulation database stored in the wave.asdb file; the simulation database contains waveforms of signals recorded by the user.

Recording signals with the "trace" command

This command traces the history of the specified signals to a simulation database file(.asdb).The default name of the simulation database is wave.asdb. By default this file is created in the current directory. The path and waveform file name can be overridden with the -asdb <file name> argument passed to the asim command.

Note: It is important to close the "wave.asdb" in Active-HDL before running any vsimsa commands or macros.

Example:

Trace all ports recursively declared in the UUT design region

# create library v_bjack
log
log hands_played
vlib v_bjack
# compile source files
# working library is specified with –work switch
vlog -work v_bjack c:/my_designs/samples_83/v_bjack/src/*.v
# initialize simulation
vsim  +access +r -c -lib v_bjack V_BJACK_tb -do 
trace -rec -ports UUT/* 
run -all
log
endsim

Trace the GEN_CLK and GEN_RES signals from the current design region

# create library v_bjack
log
log hands_played
vlib v_bjack
# compile source files
# working library is specified with –work switch
vlog -work v_bjack c:/my_designs/samples_83/v_bjack/src/*.v
# initialize simulation
vsim  +access +r -c -lib v_bjack V_BJACK_tb -do 
trace GEN_CLK GEN_RES
run -all
log
endsim

In order to be able to use the trace command you have to pass +access +r switch to the vsim command when you start the simulation:

vsim +access +r -lib v_bjack V_BJACK_tb

To minimize the impact of +access switch on the performance you can enable the read access to only a certain design region:

# create library v_bjack
log
log hands_played
vlib v_bjack
# compile source files
# working library is specified with –work switch
vlog -work v_bjack c:/my_designs/samples_83/v_bjack/src/*.v
# initialize simulation
vsim -c +access +r +p+/UUT/I11 -lib v_bjack V_BJACK_tb -do 
trace -rec -ports UUT/I11/*
run -all
log
endsim

In this case you will be able to record signals only from that design region:

trace -rec -ports UUT/I11/*

Opening the recorded simulation

To display the signals in the Waveform Viewer you need to start Active-HDL and open the newly created waveform file "wave.asdb".

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