Play Webinar

Title: Verifying Resets and Reset Domain Crossings

Description: Correct and clean reset strategy is essential for multi-million gate FPGA and ASIC devices. The possibility to start device operation from a potentially wrong state may cause malfunctions of hardware designs. Also, asynchronous resets may cause metastability effects, causing design malfunction and overheating due to increased power consumption. This webinar will describe Reset Structures and Reset Domain Crossings verification methodology and rules, demonstrated on demo designs using ALINT-PRO. The methodology behind ALINT-PRO includes careful static reset verification and ensuring valid design functionality (after resets de-assertion and an absence of metastability issues during reset assertion).


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