Play WebinarTitle: Common Testbench Development for Simulation and PrototypingDescription: Many chip design houses combine both simulation and prototyping processes to achieve the highest level of verification quality of their products. Usually, this process applies for the top-level designs. One of the issues of this approach is the inherent difference between simulation and prototyping environments. In case there is a bug found during prototyping, it is quite difficult to replicate it in the simulation environment. However, there is always a need to do so in order to properly fix the code and verify the fix in simulation. The combination of simulation and prototyping verification stages could be applied not only for top-level design, but for the block-level and IP core verification as well. Complex mission-critical IPs, forward error correction IP, etc., may require much more test stimulus than what simulation provides. In this webinar, we will outline the efficient IP design verification methodology based on the “Common Testbench” approach. The major parts of the Common Testbench could be re-used between simulation and prototyping. While reducing testbench development time, this approach helps to replicate bugs from the prototyping within the simulation environment. The Common Testbench concept will be illustrated using a design example. Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
