Play Webinar

Title: Boost VHDL Development Time with Background Design Rule Checking

Description: David Clift is an Application Specialist at FirstEDA Limited. David’s electronics engineering career started at GEC Marconi when he joined the company as an R&D engineer in 1984, working on a range of projects including Silicon-on-Sapphire and radiation tolerant ICs. David moved into the EDA industry in 1994. David is Applications Specialist for both Aldec and Sigasi. Hendrik Eeckhaut is founder and CTO at Sigasi. He has a PhD in Computer Science Engineering and did research on artificial intelligence and on FPGA design methodology for scalable video codes. In 2008 he co-founded Sigasi because he believes hardware designers deserve better tools. His mission is to help designers focus on the actual design, and automate away all distractions.


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