So, what does a vendor-independent simulator look like?

Tackle your next FPGA design with Active-HDL ™

Satyam Jani, Product Manager Software Division
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Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.


There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models, the need for vendor agnostic tools for simulation and verification has become more evident.


Efforts to verify these designs are increasing at much faster rate. Today, it is no longer sufficient to test your design by simply viewing the waveform results from simulation. Don’t you now want to run coverage analysis on your design to make sure that no parts of your design is untested? What about using assertions in your design to check the functional characteristic and behavior of the design?


If your design and simulation tools are keeping up pace with your needs then you are probably in good hands, but if they are not I invite you to join me to learn more about a cost-effective, feature-packed alternative in our upcoming webinar.


For more on Active-HDL, visit or contact

Satyam manages Aldec’s leading FPGA design entry and simulation tool – Active-HDL. He received his B.S. in Electronics Engineering from Sardar Patel University, India in 2003 and M.S in Electrical Engineering from NJIT, New Jersey in 2005.  His practical engineering experience includes areas in Solid state electronics, Digital Designing and functional verification. He has worked in wide range of engineering positions that include FPGA Design Engineer, Applications Engineer and Product Manager.


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