Averting Clock-Domain Crossing issues in FPGA Design

A solution to your worst CDC nightmare

Ajay Pradhan, Product Manager Software Division
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A failing FPGA device in the field with a Clock Domain Crossing (CDC) issue is a true nightmare. The risk of CDC related failure is on the rise as FPGA-based SOC design complexity continues to mount (thanks to an ever increasing drive to make designs faster while  reducing power consumption). Such  designs use multiple clock domains with  various parts of the design at different frequencies leading to potential signals crossing the clock domain . These CDC issues are difficult to identify in the design through simulation or timing analyses, and the very thought of the issue manifesting in the product in field is enough to send shivers down an FPGA designer’s spine!

 

The worst part is that it is nearly impossible to recreate the CDC failure in the lab. The process of “root causing” the design issue could wind up taking as much time as the design itself. Fortunately, this problem can be eliminated by “cleaning up” the design from CDC issues upfront.

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Fig. 1  Using 2 –FF synchronizers

 

Many CDC issues are perceived as metastability issues, solvable by using 2 –FF synchronizers (see Fig. 1).  However, this only confines the metastability issues.  There are host of other issues lurking such as multiple bits crossing the domain, pulse width, and signal re-convergence. All must be aggressively addressed to ensure the FPGA design is free of CDC issues.

 

There are several design techniques to address these Clock Domain Crossing issues. We can apply these design technique to address the issue only once we have found the CDC issues in the design. Finding such design holes at the earliest stage of the design cycle will save a significant amount of debug time. Consider a case where one finds a mysterious failure in the lab which appears to be an issue with CDC crossings. It would take a significant amount of time to debug versus if we could have identified the issue at the linting phase and thereafter adopted known design technique to mitigate it.  The further down the chain you identify the issue, debug time increases exponentially.

 

ALINT™ from Aldec offers the ability to perform CDC design rule checks in addition to the existing defined rule plug-ins such as STARC, DO-254 and RMM. This enables one to complete an exhaustive Design Rule Check (DRC) on an RTL design, catching issues even before getting to the verification phase. ALINT’s CDC option offers an integrated schematic viewer to precisely point out the code and relevant gates identified by CDC rule checkers. Design engineers can work more efficiently, putting their efforts upfront using known design techniques for CDC issue mitigation, thereby avoiding mysterious failures down the design cycle.

 

To learn more, visit www.aldec.com/products/alint where you’ll find downloads, configurations and training resources.

 

 

Ajay is a Product Manager at Aldec  for  DRC and CDC solutions. He received his BS  in Electrical Engineering from the National Institute of Technology, Jaipur, India and has 18 years of experience in the ASIC/FPGA and EDA industry. Ajay has worked for various companies in San Jose such as Xilinx, Mentor Graphics, Actel,  Microsemi  and Real Intent, and is experienced in roles such as as Design Engineer, Senior VLSI Engineer, Field and Corporate Application Engineering, Design Solutions, as well as building a Corporate Application Engineering Team from the bottom up as Manager of CAE at MicroSemi.

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