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Name Products Type Action
Best Practices for DO-254 Requirements Traceability   
DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. Learn in this webinar traceability best-practices for design assurance level (DAL) A FPGAs. We will provide insights to questions such as: What is the recommended approach when tracing from FPGA requirements to HDL design sources, implementation, test cases and testbench and test results? What type of output files are needed for traceability? What certification authorities look for when they review the traceability data? Play webinar   
Spec-TRACER, DO-254/CTS ウェブセミナーの録画
Common Testbench Development for Simulation and Prototyping   
Many chip design houses combine both simulation and prototyping processes to achieve the highest level of verification quality of their products. Usually, this process applies for the top-level designs. One of the issues of this approach is the inherent difference between simulation and prototyping environments. In case there is a bug found during prototyping, it is quite difficult to replicate it in the simulation environment. However, there is always a need to do so in order to properly fix the code and verify the fix in simulation. The combination of simulation and prototyping verification stages could be applied not only for top-level design, but for the block-level and IP core verification as well. Complex mission-critical IPs, forward error correction IP, etc., may require much more test stimulus than what simulation provides. In this webinar, we will outline the efficient IP design verification methodology based on the “Common Testbench” approach. The major parts of the Common Testbench could be re-used between simulation and prototyping. While reducing testbench development time, this approach helps to replicate bugs from the prototyping within the simulation environment. The Common Testbench concept will be illustrated using a design example.  Play webinar   
Riviera-PRO, ALINT-PRO, DO-254/CTS ウェブセミナーの録画
Designing Finite State Machines for Safety Critical Systems   
Finite State Machines (FSM) are a key part of safety-critical design control logic. During the operation of the FPGAs within the systems, single-event upsets or other radiation effects can cause the internal logic to flip to an incorrect value from ‘0’ to ‘1’ or ‘1’ to ‘0’ in a non-deterministic way, causing the system to fail. As transistors shrink, errors are becoming much more common; in a modern chip the devices are so small that cosmic rays or alpha particles can change the value of bits that are stored in FSM registers. In this webinar we will provide the various methods on how to develop robust and safe FSMs - from best practices in FSM design to highly reliable FSM design methods , allowing designers to develop state machines with transient errors detection and correction. Play webinar   
Riviera-PRO, ALINT-PRO, DO-254/CTS ウェブセミナーの録画
DO-254 CTS Overview   
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs.
DO-254/CTS デモンストレーションビデオ
DO-254 FPGA Level In-Target Testing   
Functional verification of digital designs in real hardware has been a serious undertaking when developing under DO-254 standard. Section 6.2 Verification Process of RTCA/DO-254 specifies that requirements must be preserved and verified from RTL simulation stage to hardware verification stage. Learn in this webinar examples of common challenges that are usually encountered during hardware verification, and more importantly, the solution to overcome these challenges. This webinar will highlight a unique methodology to replay RTL simulation in the target device at-speed that can significantly reduce the verification cycle. Play webinar   
DO-254/CTS ウェブセミナーの録画
DO-254: How to Formulate an Efficient PHAC   
With several influences on PHAC content and project specific content, this webinar will address how to write a PHAC to address DO-254 and certification authority required content. Specific examples of how to word certification basis, means of compliance, and certification liaison will be included. The webinar will demonstrate how to address tool qualification and the PLD life cycle data. Suggestions will be included for setting up the compliance data to simplify future reuse or addressing in-service changes. Play webinar   
DO-254/CTS ウェブセミナーの録画
DO-254 - How to Increase Verification Coverage by Test (Aldec and Altera)   
As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements describing FPGA I/Os must be verified by test. The problem is that testing the FPGA device at the board level provides very low FPGA I/O controllability and visibility, therefore, giving you the inability to verify specific requirements by test. In this webinar, Aldec will demonstrate how you can verify all FPGA level requirements by test. All of the requirements verified during simulation can be repeated and verified in the target device. We will demonstrate a unique solution that enables requirements-based test by reusing the testbench as test vectors for testing the device at-speed. In this webinar, Altera will also share insights into the market trends observed from different applications and discuss some of the solution strategies that will address the system reliability concerns. Play webinar   
DO-254/CTS ウェブセミナーの録画
DO-254: Requirements Optimization for Verification   
Requirements are central to DO-254 design and verification objectives. Well-formed and well-written requirements can help streamline the design and especially the verification aspects of a project. The discussion focuses on requirements and the attributes that make requirements support the design and verification processes. Play webinar   
DO-254/CTS ウェブセミナーの録画
DO-254 Requirements Traceability   
Complex custom micro-coded devices such as PLDs, FPGAs and ASICs used in commercial airborne hardware are subject to the development process outlined in the DO-254 guidance. This means that the design and verification for these types of devices must follow the strict requirements-based process described in DO-254. The primary purpose of DO-254 is to provide assurance that the device under test meets its intended functions under all foreseeable operating conditions. Requirements express the functions of the device under test, and therefore it is crucial that requirements drive the design and verification activities. Requirements traceability helps to ensure that design and verification activities are requirements-based. In this webinar, we will describe requirements traceability according to DO-254 guidance in the context of FPGAs, and we will provide explanations as to what it means for the applicants to meet the objectives for traceability. We will also describe the underlying purpose of traceability and the resulting benefits that can be achieved when done correctly. Play webinar   
Spec-TRACER, DO-254/CTS ウェブセミナーの録画
DO-254 Verification Strategies   
As a best-practice standard, efficient ASIC and FPGA project planners will allocate 1/3 of the project cycle to design and 2/3 of the project cycle to verification. The best of these planners will bias toward even more verification-hours and innovative verification strategies whenever possible, because the great reality of schedule-time allocated to verification is that THERE’S NEVER ENOUGH TIME. When an FPGA or ASIC is destined for an avionics product, effective design of that DO-254-qualified device is even more dependent-upon good verification strategies and practices. Good verification strategies will use those precious hours more effectively – and will also consistently prove to be more useful when combined with a comprehensive exploitation of well-written requirements and compliance with a well-constructed verification process, planned in advance of the work. In this webinar, we will discuss various verification strategies and how they can be applied to successful verification of a design in a DO-254 Levels A/B flow. Play webinar   
DO-254/CTS ウェブセミナーの録画
Efficient Verification Approach for DO-254 designs   
Abstract: The main purpose of DO-254 Verification Process (Chapter 6.2 of DO-254 Specification) is not merely to verify the functionality of the design but more importantly to obtain assurance that the hardware implementation meets the requirements defined in the early stages of DO-254 targeted project. It is absolutely critical to ensure that the same requirements are preserved in all stages of design and verification from planning to hardware testing. Learn in this webinar an effective approach to verifying your design from the RTL to hardware preserving the same requirements. Our experts will teach you how to use Assertions and Code Coverage for a systematic and comprehensive verification. Our experts will also demonstrate the advantages of component level verification with DO-254 CTS (Compliance Tool Set) ideal to hardware verification of Level A/B DO-254 designs. Play webinar   
DO-254/CTS ウェブセミナーの録画
Elemental Analysis: DO-254 Additional Verification for Levels A and B   
Appendix B of RTCA DO-254 describes elemental analysis as one of the possible additional verification techniques for Level A and B complex electronic hardware. Code coverage in and of itself does not always satisfy the objectives of DO-254. This presentation provides background on elemental analysis and when code coverage is sufficient for HDL based designs. The discussion will cover the various types of code coverage and which ones are relevant to certification authorities. Suggestions for resolving coverage holes will also be discussed. Play webinar   
DO-254/CTS ウェブセミナーの録画
How to plan a DO-254 compliant verification process for FPGA designs   
Verification process is crucial for DO-254 projects. Therefore, must be planned and executed with high scrutiny to provide assurance that the hardware implementation meets all safety requirements. Verification Plan together with PHAC are so important for safety, that must be submitted to the certification authority. This webinar will guide the DO-254 applicants on how to plan the process to meet DO-254 objectives and satisfy FAA and EASA expectations for the certification process.  Play webinar   
Spec-TRACER, DO-254/CTS ウェブセミナーの録画
ISO-26262 and DO-254 Achieving Compliance to Both   
Increasingly, the DO-254 industry is turning to general purpose computing platforms to implement functionality with safety of life implications. This is creating opportunities for electronics to be developed that can be used to support both avionics and automotive applications. These two domains employ somewhat similar design assurance guidelines for electronic hardware found in ISO 26262 and DO-254. Each guideline addresses safety-requirements, design activities, verification and validation, and configuration management. In addition, specific attention is paid to proving the correctness of tool operations, as well as dealing with COTS. This webinar will provide a high level introduction to both ISO 26262 and DO-254 (along with the associated regulatory considerations). Guideline similarities and differences will be addressed when complying with the various life cycle activities and objectives. Data requirements of the two guidelines will be reviewed. The guidelines’ approaches to dealing with complexity, safety requirement verification, tools, and COTS, both components and intellectual property will be highlighted. The webinar will conclude with the speaker’s thoughts on how dual compliance can be achieved. Play webinar   
DO-254/CTS ウェブセミナーの録画
Managing DO-254 Compliant Documents   
Developing Airborne Electronic Hardware for DO-254 compliance entails that applicants submit extensive professional documents and artifacts to the certification authority. The documents contain development plans and standards but also must include project data like design and verification artifacts. In addition the applicant must prove the review and change management processes are correct and reliable. One possible method to ensure the documents contain valid data and to ensure the review and change management processes are reliable is to have all project data, documents content and checklist criteria in the single repository. During this webinar we will present how to efficiently manage the DO-254 compliant documents. Play webinar   
Spec-TRACER, DO-254/CTS ウェブセミナーの録画
Managing Requirements-Based Verification for Safety-Critical FPGAs and SoCs   
Safety-critical industry standards such as DO-254 for avionics, IEC 61508/61511 for industrial and ISO 26262 for automotive enforce a requirements-based verification process to ensure that the end-product is reliable, safe and will function as intended under all foreseeable conditions. Adhering to a strict requirements-based verification approach entails that organizations must follow certain processes and provide a long list of reports and deliverables. With the growing size and complexity of today’s FPGAs and SoCs, the requirements that must be managed, reviewed, validated, traced, implemented and verified have also undeniably multiplied. Requirements frequently change impacting other project elements which leads to more rework, redesign and retests. The traceability from requirements to test data must be created and preserved so testing activities can get chaotic without a systematic method to manage it. If organizations do not have a system in place to efficiently manage these underlying activities, this translates to more time and money and unfortunately in many cases project failure. Learn in this webinar the common processes of requirements-based verification for safety-critical FPGAs and SoCs. We will describe the associated challenges, and we will show how Aldec’s tool Spec-TRACER can facilitate industry best engineering best practices to overcome these challenges. Play webinar   
Spec-TRACER, DO-254/CTS ウェブセミナーの録画
Physical Testing for DO-254   
For DAL A/B FPGAs, applicants are recommended to verify the device behavior at the silicon level (physical testing) in order to satisfy the objectives defined in RTCA/DO-254 Section 6.2.1 Verification Process. This is recommended because there are significant errors that may potentially impact safety but can only be found through physical testing. However, physical testing of the FPGA in the target board is quite challenging and not feasible in most cases. That is why both FAA and EASA allow for alternate verification means if physical tests in the target board are not feasible. Learn in this webinar a methodology that enables requirements-based physical testing with 100% FPGA I/O controllability and visibility necessary to satisfy the objectives. Play webinar   
DO-254/CTS ウェブセミナーの録画
Q & A with FAA DO-254 DER Randall Fulton (US)   
Abstract: DO-254 is officially enforced by the FAA and other worldwide certification authorities as a means of compliance for the development of airborne electronic hardware incorporating devices such as FPGAs, PLDs and ASICs. DO-254 is rapidly becoming the de-facto standard to all safety critical applications not only in avionics but also in medical, automotive and nuclear industries. Despite of its wide applications, DO-254 is still poorly understood and implementing it remains unclear. This webinar will try to provide clarifications on the most commonly misunderstood objectives of the standard. This webinar is entirely dedicated to answer your questions related to applying DO-254 to FPGAs and PLDs. Play webinar   
DO-254/CTS ウェブセミナーの録画
Satisfy DO-254 traceability requirements by using Spec-TRACER™ integration with IBM® Requirements Engineering DOORS® Next   
DO-254 requires the hardware engineers to ensure the traceability between all project artifacts starting from hardware requirements. System engineers, accordingly to the ARP4754A, have to maintain the relationships between system, hardware and software requirements, what usually is achieved by using Requirements Management solutions like IBM® Requirements Engineering DOORS® Next. Unfortunately the FPGA design artifacts like detail design, test benches and verification results are the regular files and are not maintained under the RM products. This makes it a challenge to meet the DO-254 requirements for traceability. During this presentation we will show how to manage this traceability challenge by using Spec-TRACER and its direct integration with IBM® Requirements Engineering DOORS® Next.  Play webinar   
Spec-TRACER, DO-254/CTS ウェブセミナーの録画
Shortening the verification time of safety critical projects   
For today’s designs the verification process may take much more time than the design phase. It happens especially for safety critical designs where extra objectives related to traceability, test in real hardware or robustness testing must be achieved. The solution is not only to make the simulation run faster but also to satisfy the safety critical objectives without extra workload. During this presentation we will show how you can speed up your verification phase and satisfy the verification objectives of DO-254 at a very short time by using our DO-254/CTS™ hardware verification platform.  Play webinar   
DO-254/CTS ウェブセミナーの録画
23 results (page 1/2)
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