Play Webinar

Title: Practical Co-Simulation Techniques with OSVVM Part 1: Getting Started with OSVVM Co-Simulation

Description:

OSVVM is a powerful open-source VHDL verification methodology and library widely adopted for FPGA and SoC verification. It provides a comprehensive set of capabilities including transaction-based verification, constrained randomization, functional coverage, scoreboards, memory models, reusable testbench architectures, and advanced scripting support across leading simulators such as Aldec Active-HDL and Riviera-PRO.

With the introduction of co-simulation support in OSVVM 2023.01, verification engineers can now integrate native C and C++ applications directly into VHDL simulation environments, enabling faster development and more advanced verification workflows.

In this first webinar of the series, we introduce the fundamentals of OSVVM co-simulation and demonstrate how software-driven verification can be integrated into existing OSVVM testbenches. Attendees will learn how co-simulation fits into the OSVVM framework, how to build and connect co-simulation applications, and how to compile and execute mixed-language verification environments using Riviera-PRO. Attendees will also see a live demonstration of running a JPEG image processing co-simulation test running in Riviera-PRO, highlighting practical workflows and real-world verification techniques.

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