Play Webinar

Title: Making a Simple VHDL Testbench Step-by-Step Part 1: Foundations, Architecture and Basics

Description:

Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. On top of that, they take far too much time to implement and provide close to no support when debugging potential problems.

In this first part of the 2-part webinar series, we start by looking at simulation in general and what needs to be verified for a very simple interrupt controller DUT. We will then look at the verification stages, the TB infrastructure and architecture, and verbosity control. The presentation will show how to make a simple testbench from scratch and introduce a good, modern testbench approach. We will cover logging, checking values, handling time-related aspects, and working with signal changes and stability. Commands from UVVM are introduced to show the principles and what you can and should do, but the presentation is not tool dedicated.

Rivera-PRO comes with a pre-compiled version of the latest UVVM, thus it is extremely easy to get going with UVVM after this webinar. UVVM is currently being used by more than 27% of all FPGA designers worldwide. Extensions are being developed in tight cooperation with the European Space Agency (ESA) and are thus targeted for simple but efficient verification – for both FPGA and ASIC.

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