Play Webinar

Title: HDLRegression – Automated Regression Testing for VHDL/Verilog

Description: Modern FPGA projects rely on two modes: rapid reruns of a single failing test case during development and full regression runs before milestones. Ad-hoc scripts rarely serve both; file lists, compile order, and test lists drift apart, and CI pipelines become unreliable and time-consuming. HDLRegression combines these modes with a single Python driver that handles all compilation, fully drives the simulator, and automatically builds and manages the test suite, letting you switch instantly between focused reruns and full nightly regressions. During the webinar, we turn a legacy VHDL testbench into an HDLRegression-ready testbench, let the tool build the entire test suite, and run targeted test cases from a compact Python script. You will learn how to select test cases with wildcards, organise test cases into daily or nightly test-groups for regression runs, control verbosity, and view clear pass/fail summaries for each run. After the session, you will know how to convert your own testbenches into fully automated, repeatable regression flows.

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