4.3 Constraints: Chip-Level Design Constraints

Chip-level constraints can be generated quickly and conveniently via Aldec's design constraint commands such as save_all_clocks or save_input_delays. When entered at command line or within an executable script, all relevant and detected constraints are automatically added to the active project's default constraint file. Constraints are also available for clock groups, allowing the explicit grouping of asynchronous and synchronous clock domains.

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