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Name Products Type Action
Tool Assessment and Qualification with the Aldec DO-254 Compliance Tool Set   
Abstract: The Aldec DO-254 Compliance Tool Set (CTS) provides support for the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED80) Chapter 11.4 “Tool Assessment and Qualification Process”. Aldec provides support for assessment and qualification of the design and verification tools used in the design of complex electronic hardware such as FPGA, PLD and ASIC devices.
DO-254/CTS ホワイトペーパー
Using FPGA Based Simulation Acceleration in Typical ASIC Design Flow   
Abstract: Typical ASIC front-end and back-end implementation process involves HDL simulation as a method of verifying design netlist functionality at each stage of the flow. Although HDL simulation is considered accurate it suffers from very low execution speed.Aldec provides the DVM software that allows reusing your existing FPGA prototyping board as a platform for hardware acceleration of HDL simulation.
HES-DVM, HES™ FPGA Boards ホワイトペーパー
Using FPGA Prototyping Board as an SoC Verification and Integration Platform   
Abstract: Size of new designs has grown so much that it easily allows creation of the entire system containing microprocessor unit and peripherals on one chip. Verification of such designs can no longer rely on software only, since simulation of MPU does not allow fast enough testing of application software and formal tools handle system hardware only. The use of FPGA-based prototyping boards creates fast and economical solution to this problem. This paper presents one practical implementation of Prototyping Board Verification and Integration Platform.
HES-DVM, HES™ FPGA Boards ホワイトペーパー
Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms   
The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it.
Riviera-PRO ホワイトペーパー
Vector Implementation of Integer Arithmetic in VHDL   
Digital circuit designer very frequently faces the dilemma: how to implement arithmetic operations in his or her design. This article presets balanced solutions that provides high level of functionality and maintains decent readability of the code.
Active-HDL ホワイトペーパー
Verification of Ethernet Designs with SCE-MI based Aldec Emulator   
Abstract: This white paper presents how to use modern verification techniques for advanced ASIC and SoC designs. Network based application has been selected for this study as a real life design project. Verification process will be performed using Aldec hardware emulation system called HES with transaction based SCE-MI interface used for testing activities. The key objective is to perform the verification of the Ethernet Network Switch with real data delivered directly from Ethernet network in very limited time assigned for verification setup process.
HES-DVM, HES-7 ホワイトペーパー
Verification of Multirate Systems with Multiple Digital Blocks   
Modern RF system designs require extensive digital signal processing and flexibility to fulfill the current and coming standards. Systematically growing set of functions implemented on SoC pushes system architects and hardware designers to look for methodologies, which would enable efficient co-design and co-verification. In this paper, we will be discussing the challenges associated with simulating multirate system-level designs that include multiple digital blocks.
Riviera-PRO ホワイトペーパー
Virtual Modeling with Aldec and Imperas   
Abstract: Virtual platforms play a significant role in system level development, but they require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP™ (Open Virtual Platforms) and OVPsim™ (OVP simulator). Hardware and Software design teams are now able to simulate and debug virtual models of processors, memories and peripherals while the rest of the system resides in the emulator board running at MHz clock speeds.
HES-DVM, HES-7 ホワイトペーパー
Xilinx Zynq-based Development Platform for ADAS    
ADAS is an essential step between initial DA (Driver Assistance) systems and fully autonomous cars capable of driving without human guidance. Aldec provides an FPGA-based development platform powered by Xilinx Zynq-7000 SoC/FPGA heterogeneous technology, as well as a set of ADAS-class reference designs for rapid development of current and next-generation ADAS solutions for the automotive market.
Riviera-PRO, TySOM™ EDK ホワイトペーパー
大容量FPGAデバイスの最適設計手法   
最新のFPGA技術の進歩と大規模FPGAデバイスのリリースにより、デザインチームは高品質のHDLコードを作成する際に今まで以上に多くの課題に直面しています。機能検証と実装段階で時間を節約するためには、デザインプロセスの初期段階から設計の品質を確保することがますます重要になります。ASICの設計フローでは、Lintツール(デザインルールチェッカーと呼ばれることもあります)は、設計ライフサイクルの初期段階で設計品質を保証し、プロジェクトライフサイクル全体にわたってこの品質を維持します。
Riviera-PRO, ALINT-PRO ホワイトペーパー
50 results (page 3/3)
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