SemiWiki: Aldec Adds Simulation Acceleration for Microchip FPGAsDate: 2020/11/10 Type: In the Newsby Tom Simon Despite the fact that FPGA based systems make it easy to add ‘hardware in the loop’ for verification, the benefits of HDL and gate level simulation are critical for finding and eliminating issues and bugs. The problem is that software simulators can require enormous amounts of time to run full simulations over sufficient time intervals to locate and eliminate problems. This is where HDL simulation acceleration can help close the gap and improve productivity. Aldec has a white paper titled “HDL Simulation Acceleration Solution for Microchip FPGA Designs” that discusses the topic in detail and provides insight into how designers can gain the benefits of speedup from hybrid software and hardware based simulation acceleration to rapidly identify and resolve issues. Simulation Acceleration FPGA based systems are heavily used in aerospace, aviation, and automotive markets. Some of these markets have very specific requirements for reliability and radiation tolerance (RT). FPGAs, such as those from Microchip offer excellent solutions for these markets. Microchip’s PolarFire FPGA offers RT and their SmartFusion2 comes with an embedded ARM Cortex-M3. The Aldec paper covers each of the verification processes that must be addressed. There is RTL simulation with all the necessary test benches. Then comes post-synthesis simulation, which comes with much more simulation overhead. This is also when any potential discrepancies between gate level and RTL results are examined. Also, IP cores which should be independently verified need to be simulated in-system to ensure proper integration. As always there are regression tests that must be performed throughout the project lifetime. On top of this there is the use of constrained random testing to catch difficult to find corner cases. Constrained random testing usually needs massive amounts of simulation. Lastly, any debugging requires problem identification, fix implementation and verification which calls for the features found in HDL simulation. In the white paper Aldec describes their solution for hardware acceleration of simulation of FPGA based system – HES-DVM. It offers simulation acceleration, emulation and physical prototyping. In the case of special purpose applications like RT or where there is vendor specific IP, they offer the ability to use the target FPGA for simulation. This means that IP can run natively using specialized features of the FPGA during simulation. The test benches and any HDL needed for debugging run on the Aldec Riviera-PRO or Active-HDL HDL simulators which are tightly integrated or with other simulators using PLI or VHPI interfaces. This approach requires no changes to testbenches because the DUT-wrapper handles the connection between the HDL simulator and the simulation running on the HES board. For the rest of this article, please visit SemiWiki.