SemiWiki: RAL, Lint and VHDL-2018Date: 2018/08/08 Type: In the Newsby Alex Tan Finite state machines (FSMs) are widely adopted as part of reactive systems to capture their dynamic behaviors using a limited number of modes or states that usually change according to the applied circumstances. Some terminologies are frequently used to describe the FSM characteristics: state, transition, condition and sequences. A state defines the behavior and may produce action or output; a transition describes change involving of state(s); a condition allows transition to occur; and a sequence is comprised of a set of two or more transitions. FSM can be categorized in term of its output transition. A deterministic FSM, if it has only one transition to next state; while a non-deterministic FSM has more than one possible next state for each pair of current state and input vectors. Article: Mobile SoCs: Two Cores are Better Than Four?-caption2.pngFor practical applications, FSMs can be grouped based on how their outputs are defined. Moore FSM is the state machine whose output are a function of the current state only, while a Mealy FSM has its output and next state dependent on both the current state and input(s). Many of the FSM practical applications such as in communication systems, crypto-processing, visual processing and as part of the embedded controllers are implemented using various schemes, from a static to be more reconfigurable styles --depending on if it is internally initiated (self-reconfigurable) or driven by external reconfiguration events. Aldec and Verification of FSM As an industry leader in Electronic Design Verification, Aldec’s solutions include a verification strategy in ALINT-PRO™ that is comprised of three key elements: static structural verification, design constraints setup, and dynamic functional verification. The first two steps are executed in ALINT-PRO, while dynamic checks are implemented via integration with Aldec’s simulators Riviera-PRO™ and Active-HDL™ (ModelSim® is supported) based on the automatically generated testbench. For the rest of this article, please visit SemiWiki.