Top White Paper Downloads from 2013

Date: 2014/01/16
Type: Release

Henderson, NV – January 15, 2014 – As a global leader in Design Verification, Aldec, Inc. offers industry-leading Products, Support, Training, and Resources. The Aldec Support Center boasts thousands of App Notes, Tutorials*, Recorded Webinars* and White Papers* to help engineers get up to speed quickly.


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01_img_011614_plots-for-debugging_145Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms

The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient …



02_img_011614_increasing-verification-coverage-by-test_145DO-254: Increasing Verification Coverage by Test

Verification coverage by test is essential to satisfying the objectives of DO-254. However, verification of requirements by test during final board testing is challenging and time-consuming. This white paper explains the reasons behind these challenges, and provides recommendations how to overcome them. The recommendations …



03_img_011614_randomization-and-functional-coverage-in-vhdl_145Randomization and Functional Coverage in VHDL

Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.



04_img_011614_corporate-standardization-fpga-design-flow_145Corporate Standardization of FPGA Design Flow

Growing customer requirements and technological abilities increase the design complexity of hardware and software. Time to market is shortening as well as the lifetime of new designs. In order to meet all those requirements a new approach to the design process is required.




05_img_011614_making-floating-point-arithmetic-work-in-your-rtl-designs_145Making Floating-Point Arithmetic Work in Your RTL Design

Description: Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This …



About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

Media Contact: Aldec, Inc.                               
Christina Toole, Corporate Marketing Manager
+ (702) 990-4400
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