Aldec @ DAC 2013: Advanced Verification, HW/SW Emulation, SoC/ASIC Prototyping and more
Design Automation Conference (DAC), Austin, Texas – May 15, 2013 – Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for FPGA and ASIC devices, will offer Technical Sessions and Demonstrations June 3-5, 2013 at Booth #2225 at this year’s Design Automation Conference (DAC) in Austin, Texas.
Daily (June 3-5, 2013) at Aldec’s Booth #2225
Session 01: Prototyping Over 100 Million ASIC Gates Capacity
Session 02: Hybrid SoC Verification and Validation Platform for Hardware and Software Teams
Session 03: Requirements Traceability for Safety-Critical FPGA/ASIC Designs
Session 04: Comprehensive CDC Analysis for Glitch free Design
Session 05: UVM/SystemVerilog: Verification and Debugging
Session 06: VHDL 2008 and Beyond: OS-VVM Continues to Grow
Session 07: Accelerate DSP Design Development: Tailored Flows
Session 08: Ask Aldec: Demos, Roadmaps, Partners, Q&A, etc.
Session 09: CyberWorkBench: C-based High Level Synthesis and Verification
Wednesday, June 5, 2013, 2:00-4:00pm
Austin Conference Center, Room 17AB
Complete Abstracts and Registration available at www.aldec.com/dac2013.
DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP). www.dac.com
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
|Media Contact:||Christina Toole, Aldec, Inc.