DSP Survey, Solutions and Resources

Date: 2013/04/04
Type: Release


Shaping the Future of ASIC/FPGA DSP Design Flow – Take survey

DSP Designers Survey

Aldec is conducting a brief survey through April 30, 2013, to better address the challenges and requirements faced by DSP designers in the field.
As a thank you, a random drawing will be held among survey participants to receive a $100 Amazon giftcard.

Fastest Co-Simulation Interfaces for MATLAB®, Simulink®, SystemVue®

CoSimulation Interfaces

Aldec Riviera-PRO™ offers the fastest direct co-simulation interfaces with MathWorks MATLAB® & Simulink® and Agilent SystemVue®, enabling multi-domain electronic system-level (ESL) design flow for DSP, RF, and FPGA/ASIC design.

Related Application Notes:

MATLAB – HDL Interface in Riviera-PRO and Active-HDL

Controlling Riviera-PRO from MATLAB

Using Agilent SystemVue® Co-Simulation Interface

FPGA Prototyping Using Agilent SystemVue and Aldec Riviera-PRO

DSP-Aware Debugging Tools

There are two types of Independent Design Environments (IDE) – those with and those without DSP-aware debugging tools. When an IDE does not provide DSP- aware debugging tools, engineers must use workarounds in the design process instead of focusing their attention on DSP concepts and improving productivity.


See Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms
to uncover the benefits of the new Plot Window to debug data-intensive applications such as image processing, digital filtering, industrial control systems, telecommunication systems and certain embedded systems.


Designs that use IEEE 754-2008™ floating-point arithmetic present another debugging challenge. The white paper, Making Floating-Point Arithmetic Work in Your RTL Design explains how to tackle floating-point arithmetic debugging challenges using the tools available with Riviera-PRO IDE.

Forward to a Friend


Related  Resources

Upcoming Events:

Aldec and Agilent Joint DAC Tutorial, Wireless Algorithm Validation from System to RTL to Test


White Paper:

Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms


White Paper:

Making Floating-Point Arithmetic Work in Your RTL Design


Free Evaluation:

Riviera-PRO Advanced Verification Platform


Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.