Event Details

Time: 4:00 PM - 5:00 PM (CEST)

 

Webinar Overview

Vivado Block Designs based on the AMD Zynq UltraScale+ MPSoC can be difficult to verify at the system level when the Processing System (PS) must initiate and respond to AXI transactions, provide memory access, and interact with programmable logic peripherals. This webinar presents a VHDL/OSVVM approach that replaces the PS8 instance during simulation with a behavioral interface model while preserving the original PS8 ports and the synthesizable design structure.

The replacement model uses OSVVM AXI4 and UART Verification Components together with Virtual Transaction Interfaces (VTIs). VHDL configurations bind the simulation model in place of the PS8, while VTI and VHDL external names allow the test controller to access verification components embedded inside the Vivado-generated Block Design hierarchy. The PS8 replacement provides clock and UART behavior, AXI managers for PS-to-PL transactions, and AXI memory models for PL-to-PS accesses.

Using the open-source BigDesign reference design, this webinar demonstrates the resulting OSVVM testbench architecture in Riviera-PRO, including AXI-controlled peripherals, UART testing, memory traffic, and direct access to the simulated memory for verification. This webinar also presents Riviera-PRO performance improvements for simulating large OSVVM memory models. This approach enables the surrounding Vivado Block Design and PL logic to be exercised without modeling the internal processor subsystem, providing a practical VHDL-native verification flow for OSVVM users.

 

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