Event Details

Leveraging 64-bit Integers - Range, Precision, OSVVM AXI and Big Memories for VHDL Designs (FPGA Conference Europe)
Date: Wednesday, July 1, 2026

Time: 5:20 p.m. – 6:00 p.m. (CEST)

Building upon the previous seminar, "Simulating Big Memories using OSVVM’s Memory Model" by Patrick Lehmann and  Adrian Weiland, this session explores the technical advantages of the VHDL-2019 integer expansion.

Historically, VHDL's 32-bit integer limit forced workarounds for high-capacity memory modeling and high-frequency timing. With VHDL-2019 now mandating a minimum 64-bit range for the INTEGER type—and support already live in tools like Riviera-PRO—new simulation possibilities have emerged.

In collaboration with the PLLC2  team, we will demonstrate:

Architectural Shifts: How the transition to 64-bit integers simplifies the modeling of massive datasets and address spaces.

Practical Implementation: An inside look at the PLLC2team’s design, utilizing OSVVM models specifically adapted for the 64-bit range.

Performance Optimization: Strategic hints on improving simulation throughput and memory management in modern VHDL environments.

Level: Beginner