Event Details View All Recorded Events Date Event Type 場所 Action Jun 04, 2026 Making a Simple VHDL Testbench Step-by-Step Part 2: BFMs and Simplifications, Demo, and Debugging (EU) Time: 4:00 PM - 5:00 PM (CEST) Webinar Overview Building on the fundamentals and the DUT from Part 1, this session introduces register access and Bus Functional Models (BFMs), including how to design reusable and simplified BFMs for easier reuse and better productivity. We will also see how time-related aspects in our DUT can be verified. A live and interactive demo will showcase how structured logging, error handling, and progress reporting can significantly improve debugging efficiency. Attendees will also see how UVVM enables quick adoption of these techniques, especially with tools like Rivera-PRO that include precompiled support of UVVM. Rivera-PRO comes with a pre-compiled version of the latest UVVM, thus it is extremely easy to get going with UVVM after this webinar. UVVM is currently being used by more than 27% of all FPGA designers worldwide. Extensions are being developed in tight cooperation with the European Space Agency (ESA) and are thus targeted for simple but efficient verification – for both FPGA and ASIC. Agenda: Register access and BFMs Creating reusable procedures and simplifying BFMs Completing the test case Interactive Demo (debugging with effective messages and reports) Summary Q&A Presenter BIO Espen Tallaksen, CEO of EmLogic, NorwayEspen is also the author and architect of the Open Source UVVM (Universal VHDL Verification Methodology), andhas a strong interest in methodology cultivation and pragmatic efficiency and quality improvement.He has given lots of technical presentations at various international conferences with great feedback. He is also giving courses on FPGA Design and Verification worldwide. ウェブセミナー Online More Info
