As you know, UVM has spread out dynamically in recent years as engineers begin to see the benefits of constrained-random verification techniques. Unfortunately, increased productivity and better quality of taped-out designs is being ransomed by the demand for high performance simulation platforms. Thus, simulation acceleration becomes irreplaceable in order to keep pace with this productivity growth. We invite you to join us at DAC, where our engineers will share how a scalable, FPGA hardware platform and “Swiss army knife” DVM software that can easily compile a design and integrate simulation acceleration interfaces to fit seamlessly in the existing simulation environment. Session 05: UVM Simulation Acceleration in FPGA Prototyping Board. Design Automation Conference (DAC 2015) Moscone Center, San Francisco, CA June 7-11, 2015 | BOOTH #1725 Visit http://www.aldec.com/dac2015 to register for a session of your choice, and be sure to join us Monday night at DAC from 5-6pm for cocktails at Booth #1725. Attend a session at Aldec Booth#1725 and enter to win a DJI Phantom Drone Quadcopter w/ GoPro Camera! Drawing to take place Monday night at the Aldec Cocktail Reception from 5-6pm, Booth #1725. Did you see our recent press release? Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification. Aldec is enabling FPGAs to accelerate even the largest verification tasks, while bringing unparalleled capacity to FPGA-based prototypes. Aldec is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. +1.702.990.4400 sales@aldec.com www.aldec.com Don't want to receive email Updates? Unsubscribe here.
