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1.0 Basics: Installation and Setup   
This video will show you how to install and setup the main ALINT-PRO application as well as additional rule plug-ins. Installation of extra rulesets can be confirmed within the main tool and enabled via the policy editor. For license verification during setup, the license diagnostic tool provides ample information on the current license file and licensed modules.
ALINT-PRO Demonstration Videos
1.1 Basics: Running Design Entry and Linting   
ALINT-PRO's Flow Manager window allows managing the design analysis process in a convenient way. This video will show each step of the design flow, going through parse, elaboration, synthesis, constraints, and finally linting. At each step, more information about a project can be obtained. Additionally, each step includes various settings and configurable properties that allow for a highly customized linting process.
ALINT-PRO Demonstration Videos
1.2 Basics: Importing and Running Other Designs   
Whether one chooses to develop their design in Active-HDL, Riviera-PRO, Quartus, or Vivado, ALINT-PRO can always be used to perform design rule checking via the tool's convert feature. Converting external project files into ALINT-PRO turns the source project files into the equivalent ALINT-PRO workspace and project structure. Once converted, the design is then accessible to all of the solution's linting and rule checking features.
ALINT-PRO Demonstration Videos
1.3 Basics: Violation Viewer and Reports   
ALINT-PRO's violation viewer provides a user friendly window for displaying and managing design rule violations. Coupled with automatic report generators, the tool helps not only to identify any violations within your design, but also document them so that they may be corrected and even prevented in later designs. Automatic report generators come in a number of formats, including CSV, PDF, HTML, as well as Quality Reports which provide metrics on how compliant a design is to a given rule set.
ALINT-PRO Demonstration Videos
1.4 Basics: Workspaces, Projects, and Libraries   
Workflow in ALINT-PRO is organized through projects that are grouped into workspaces. A project will contain the set of properties and files, those being your HDL source code and design constraints, to form a single entity that makes up part of your design. Libraries are automatically generated at the local level and correspond to projects within the workspace. Additional libraries can be added through the tool's library export and attach features.
ALINT-PRO Demonstration Videos
1.5 Basics: Policy Editor   
The quality of linting results is largely dependent on one's policies and rules. Through the use of its policy editor, ALINT-PRO provides an effective means of managing and customizing those policies and rules to best fit the standards and practice of one's design team or company.
ALINT-PRO Demonstration Videos
1.6 Basics: Waivers   
Waivers provide an excellent service in managing violations during the linting process by ignoring those violations or sources of violations that might be too pessimistic for or not applicable to one's design. ALINT-PRO's interface provides an easy process for adding and removing these waivers no matter the source. Additionally, the tool's waiver editor provides a single location where one can manage and edit an entire project's waiver list, and even export this list for future projects.
ALINT-PRO Demonstration Videos
1.7 Basics: Schematic Cross-Probing for Netlist Issues   
Through the RTL Schematic Window, ALINT-PRO provides a powerful graphical representation of a design's netlist. This window can be accessed, or cross-probed, from various other windows within the tool, which focuses on and highlights those different sources.
ALINT-PRO Demonstration Videos
2.1 Console: Command Line Batch Modes    ALINT-PRO Demonstration Videos
2.2 Console: Compatibility Commands    ALINT-PRO Demonstration Videos
3.1 External Tools: Launching from Active-HDL   
Linting can be ran directly from your design tool using the "Run In Aldec ALINT-PRO" feature available in Active-HDL. This feature can either generate a new tcl script that automatically converts the design workspace and performs linting or can use an existing script to perform after launching the ALINT-PRO software.
ALINT-PRO Demonstration Videos
3.2 External Tools: Launching from Riviera-PRO   
Linting can be ran directly from your simulation tool using the "Check in Aldec ALINT-PRO" feature available in Riviera-PRO. This feature can either generate a new tcl script that automatically converts the design workspace and performs linting or can use an existing script to perform after launching the ALINT-PRO software.
ALINT-PRO Demonstration Videos
4.1 Constraints: Block-Level Design Constraints   
In projects with encrypted IP, unimplemented components, or simply missing libraries, it is necessary to add block-level design constraints to ensure proper linting of your design. Constraints can be applied to those black box components where internal logic is unreachable and provides the tool with the much-needed information on how that module operates. This behavior is passed by setting cell and pin types, or simply using one of the built-in lib function for common components.
ALINT-PRO Demonstration Videos
4.2 Constraints: Library Functions and More    ALINT-PRO Demonstration Videos
ALINT-PRO 4.4 Constraints: Automatic Generation    ALINT-PRO Demonstration Videos
Boost VHDL Development Time with Background Design Rule Checking   
David Clift is an Application Specialist at FirstEDA Limited. David’s electronics engineering career started at GEC Marconi when he joined the company as an R&D engineer in 1984, working on a range of projects including Silicon-on-Sapphire and radiation tolerant ICs. David moved into the EDA industry in 1994. David is Applications Specialist for both Aldec and Sigasi. Hendrik Eeckhaut is founder and CTO at Sigasi. He has a PhD in Computer Science Engineering and did research on artificial intelligence and on FPGA design methodology for scalable video codes. In 2008 he co-founded Sigasi because he believes hardware designers deserve better tools. His mission is to help designers focus on the actual design, and automate away all distractions.  Play webinar   
ALINT-PRO Recorded Webinars
Design Rule Checking (DRC) for Common SystemVerilog Design Mistakes   
Due to the size and complexity of current hardware design, design verification tasks can become increasingly complex and lengthy. Recent advancements in hardware design have focused on cleaning up design code as much as possible prior to entering the design verification stage. Unfortunately, such design code cleanup performed during relatively short time may significantly reduce overall design verification time and effort. As SystemVerilog design constructs gain popularity among hardware designers, it is increasingly important to assist designers with Systemverilog design code verification and cleanup. ALINT-PRO™ is a design verification solution for SystemVerilog, Verilog and VHDL RTL code. It is able to statically verify and cleanup the code far beyond compiler-level checks. It is capable of statically verifying most of the popular SystemVerilog design constructs, uncovering some of critical design issues early in the design cycle.  Play webinar   
ALINT-PRO Recorded Webinars
Efficient CDC Debugging Using Phase-based Methodology for Large FPGA/ASIC Multi-clock Designs    
Presenter: Sergei Zaychenko, Aldec Software Product Manager

Noise reduction is a key trend in currently available Clock Domain Crossing (CDC) Verification solutions. Most CDC tools on the market are unable to extract clocking and reset structures that match the original designer's intent. The designs often contain hundreds of vendor-specific blocks and 3rd-party IPs with unclear clock/reset relations. The timing of external interfaces might not be clearly defined, affecting the CDC results. Multiple clock modes, false paths and custom in-house synchronizers are not making CDC analysis any easier.

A user must typically go through several rounds of tool configuration, policy adjustments, clock/reset constraints refinements, description of timing intent for the black boxes. Bringing the focus to concrete configuration/constraint issues is challenging when forced to browse through thousands of violation messages and full schematics. Much time and effort might be lost on cleaning the configuration through printed CDC end-results, instead of keeping initial focus on correct control structures. In additional, an incorrect/incomplete configuration often leads to poor CDC tool performance.

In this webinar, learn how a seamless, phased-based CDC debugging methodology can reduce overall CDC signoff time.  Play webinar   
ALINT-PRO Recorded Webinars
Eliminating Clock Domain Crossing (CDC) Issues Early in the Design Cycle   
In this webinar, we’ll discuss typical synchronizer structures to put in place for CDC crossings as well as the most common mistakes in their structure. We’ll also cover some of the functional problems that often arise due to incorrect synchronization, as well as how to verify a project against CDC issues during the RTL design and RTL simulation design stages. Play webinar   
ALINT-PRO, ALINT-PRO-CDC Recorded Webinars
Fast Track to ALINT-PRO: Design Entry and Linting    
ALINT-PRO is a design verification solution for RTL code focused on general issues analysis including: RTL and post-synthesis simulation mismatches, design coding for optimal synthesis, avoiding problems on further design stages, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design time dramatically. This "Fast Track" series webinar is designed to help engineers get up to speed quickly with ALINT-PRO. Learn how to prepare designs for analysis in ALINT-PRO and obtain linting results. We also cover workspace and project setup, library management, linting configuration, and violation analysis. Play webinar   
ALINT-PRO Recorded Webinars
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